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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chae, Chuck | - |
| dc.contributor.author | Heo, Wonje | - |
| dc.contributor.author | Shin, Donghoon | - |
| dc.date.accessioned | 2025-12-24T13:40:11Z | - |
| dc.date.available | 2025-12-24T13:40:11Z | - |
| dc.date.created | 2025-10-30 | - |
| dc.date.issued | 2025-12 | - |
| dc.identifier.issn | 2372-2541 | - |
| dc.identifier.uri | https://scholar.dgist.ac.kr/handle/20.500.11750/59278 | - |
| dc.description.abstract | Conventional steganography techniques based on Pixel Intensity Decomposition (PID) suffer from a critical 'pixel jump' problem that severely limits payload capacity, creating a major obstacle to achieving high-capacity data hiding. To address this challenge, this paper proposes a novel high-capacity image steganography technique, termed the Quotient and Remainder (QR) method, which provides a unified framework for robust k-LSB embedding by integrating PID with an advanced Pixel Indicator Technique (PIT). The proposed method introduces a dynamic virtual bit plane construction using an optimized integer sequence in conjunction with a novel bit-plane congruence matrix (BPCM). By leveraging quotient and remainder operations, this approach minimizes embedding distortion, enables unique and accurate data extraction, and significantly enhances payload capacity while preserving high imperceptibility in stego images. Experimental results for k = 3, 4, and 5 demonstrate that the QR method achieves an outstanding balance between capacity and imperceptibility, yielding embedding capacities of 6, 8, and 10 bits per pixel (bpp), respectively, while maintaining excellent PSNR values of 44.68, 40.48, and 35.37 dB. The proposed framework is also robust against common steganalysis attacks and well-suited for secure IoT applications where high payload efficiency and visual fidelity are essential. | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | QR: Modular Arithmetic-Enhanced Virtual Bit Plane Construction for High-Capacity Image Steganography | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1109/JIOT.2025.3615138 | - |
| dc.identifier.wosid | 001621293300044 | - |
| dc.identifier.scopusid | 2-s2.0-105017786911 | - |
| dc.identifier.bibliographicCitation | IEEE Internet of Things Journal, v.12, no.23, pp.51483 - 51496 | - |
| dc.description.isOpenAccess | FALSE | - |
| dc.subject.keywordAuthor | Data hiding | - |
| dc.subject.keywordAuthor | pixel indicator technique (PIT) | - |
| dc.subject.keywordAuthor | pixel intensity decomposition (PID) | - |
| dc.subject.keywordAuthor | steganalysis | - |
| dc.subject.keywordAuthor | steganography | - |
| dc.subject.keywordAuthor | virtual bit planes | - |
| dc.citation.endPage | 51496 | - |
| dc.citation.number | 23 | - |
| dc.citation.startPage | 51483 | - |
| dc.citation.title | IEEE Internet of Things Journal | - |
| dc.citation.volume | 12 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science; Engineering; Telecommunications | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems; Engineering, Electrical & Electronic; Telecommunications | - |
| dc.type.docType | Article | - |
Department of Electrical Engineering and Computer Science