Detail View

  Department of Electrical Engineering and Computer Science Theses Ph.D.

Optimization of Structural Design for Vertically Stacked Plate-Type Transistors

Citations

WEB OF SCIENCE

Citations

SCOPUS

Metadata Downloads

XML
Excel
DC Field Value Language
dc.contributor.advisor 장재은 -
dc.contributor.author Goeun Pyo -
dc.date.accessioned 2026-01-23T11:00:22Z -
dc.date.available 2026-01-23T11:00:22Z -
dc.date.issued 2025 -
dc.identifier.uri https://scholar.dgist.ac.kr/handle/20.500.11750/59795 -
dc.identifier.uri http://dgist.dcollection.net/common/orgView/200000893522 -
dc.description Vertically stacked transistor, vertical transistor, dual-gate vertical transistor, memorable vertical transistor, nano channel length -
dc.format.extent 123 -
dc.language eng -
dc.publisher DGIST -
dc.title Optimization of Structural Design for Vertically Stacked Plate-Type Transistors -
dc.title.alternative 수직 적층형 판상 트랜지스터 구조 설계 최적화 -
dc.type Thesis -
dc.identifier.doi 10.22677/THESIS.200000893522 -
dc.description.degree Doctor -
dc.contributor.department Department of Electrical Engineering and Computer Science -
dc.contributor.coadvisor Jaehong Lee -
dc.date.awarded 2025-08-01 -
dc.publisher.location Daegu -
dc.description.database dCollection -
dc.citation XT.ID 표15 202508 -
dc.date.accepted 2025-07-21 -
dc.contributor.alternativeDepartment 전기전자컴퓨터공학과 -
dc.subject.keyword Vertically stacked transistor, vertical transistor, dual-gate vertical transistor, memorable vertical transistor, nano channel length -
dc.contributor.affiliatedAuthor Goeun Pyo -
dc.contributor.affiliatedAuthor Jae Eun Jang -
dc.contributor.affiliatedAuthor Jaehong Lee -
dc.contributor.alternativeName 표고은 -
dc.contributor.alternativeName Jae Eun Jang -
dc.contributor.alternativeName 이재홍 -
dc.rights.embargoReleaseDate 2028-08-31 -
Show Simple Item Record

File Downloads

  • There are no files associated with this item.

공유

qrcode
공유하기

Total Views & Downloads

???jsp.display-item.statistics.view???: , ???jsp.display-item.statistics.download???: