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Design Of Pipelined SAR ADC For Wireline Data Communications
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dc.contributor.advisor 김가인 -
dc.contributor.author Heewon Sung -
dc.date.accessioned 2026-01-23T11:02:46Z -
dc.date.available 2026-01-24T06:00:44Z -
dc.date.issued 2025 -
dc.identifier.uri https://scholar.dgist.ac.kr/handle/20.500.11750/59837 -
dc.identifier.uri http://dgist.dcollection.net/common/orgView/200000890092 -
dc.description SAR ADC, pipelined SAR, loop-unrolled architecture, comparator calibration, wireline communication -
dc.description.abstract This thesis presents the design of high-speed, low-power successive approximation register (SAR) analog-to-digital converters (ADCs) for wireline data communication systems. First, an 8-bit loop-unrolled SAR ADC was designed and fully implemented in a 28nm CMOS process to establish a scalable and efficient architecture. The converter operates at 1 GS/s and integrates eight asynchronous common-stage blocks with background offset calibration. Post-layout simulations show that the 8-bit ADC achieves an effective number of bits (ENOB) of 6.73 while consuming 3.47 mW from a 0.9 V supply. Building on this modular design, a 10-bit pipelined SAR ADC architecture is then proposed to support higher resolution. This two-stage architecture reuses the core components of the 8-bit ADC and introduces a self-timed clocking scheme for interstage residue amplification. This thesis details the architectural and schematic-level design of the 10-bit ADC. While the full system performance verification remains as future work due to the incomplete implementation of the interstage amplifier, the proposed structure demonstrates a viable path toward scalable, high-resolution ADCs. Keywords: SAR ADC, pipelined SAR, loop-unrolled architecture, comparator calibration, wireline communication|본 논문에서는 유선 통신 시스템을 위한 고속, 저전력 아날로그-디지털 변환기를 설계하였다. 제안된 구조는 두 가지 ADC 아키텍처로 구성된다. 첫 번째로, 빠른 속도와 고효율 달성을 위해 loop-unrolled 방식으로 8비트 SAR ADC를 구현하였고, 두 번째로 이를 기반으로 분해능 향상을 위해 10비트 파이프라인 SAR ADC 구조를 제안하였다.
8비트 loop-unrolled SAR ADC는 비교기의 병렬 동작과 비동기식 로직을 기반으로 높은 샘플링 속도를 달성하였고, 내장된 오프셋 보정 회로를 통해 정확도를 향상시켰다. 이 구조는 TSMC 28nm HPC+ 공정에서 구현되었으며, 0.9V 동작 전압 및 500 mVpp,diff입력 조건에서 유효비트수(ENOB) 6.73비트를 달성하였다.
10비트 파이프라인 SAR ADC는 첫 번째 스테이지에서 상위 비트를 변환하고, 그 결과를 증폭하여 두 번째 스테이지에서 나머지 하위 비트를 변환하는 구조로 설계되었다. 본 논문에서는 회로 구성 및 스테이지 간 동작 타이밍에 대한 상세 설계를 수행하였으나, 증폭기 구현이 완료되지 않아 전체 시스템의 성능 검증은 향후 과제로 남겨두었다. 제안된 구조는 확장성 있는 고해상도 ADC의 구현 가능성을 제시한다.
핵심어: SAR ADC, pipelined SAR, loop-unrolled architecture, comparator calibration, wireline communication
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dc.description.tableofcontents Ⅰ. Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Organization 2

ⅠⅠ. Background of SAR ADCs 3
2.1 Operating Principle of SAR ADCs 3
2.2 ADC Performance Metrics 4
2.3 Non-Idealities in SAR ADCs 6
2.3.1 Quantization Noise 6
2.3.2 Thermal Noise (kT/C Noise) 6
2.3.3 Sampling Jitter 7
2.4 High-Speed SAR ADC Design Techniques 8
2.4.1 Asynchronous SAR ADC 8
2.4.2 Top-Plate Sampling and Monotonic Switching 8
2.4.3 Split Monotonic Capacitor Switching 9
2.4.4 Loop-Unrolled SAR ADC 11
2.4.5 Pipelined SAR ADC 12

III. 8-bit Loop-Unrolled SAR ADC Design 14
3.1 System Architecture Overview 14
3.2 Circuit Implementation 15
3.2.1 Bootstrapped Switch 15
3.2.2 CDAC 17
3.2.3 Common Stage Architecture 19
3.2.3.1 Comparator Offset Calibration 19
3.2.3.2 Clock Logic 23
3.2.3.3 Memory Cell 24
3.3 Layout and Tape-Out Summary 25
3.4 Measurement Setup 28
3.5 Simulation Results of the 8-bit Loop-Unrolled SAR ADC 29
3.6 Conclusion 32

IV. 10-bit Pipelined SAR ADC Design 33
4.1 Architecture Overview 33
4.2 Amplification Timing and Clock Generation 34
4.3 Interstage Amplifier 36
4.4 Conclusion 36
4.5 Future Work 37
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dc.format.extent 40 -
dc.language eng -
dc.publisher DGIST -
dc.title Design Of Pipelined SAR ADC For Wireline Data Communications -
dc.title.alternative 유선 통신용 파이프라인 SAR ADC 설계 -
dc.type Thesis -
dc.identifier.doi 10.22677/THESIS.200000890092 -
dc.description.degree Master -
dc.contributor.department Department of Electrical Engineering and Computer Science -
dc.contributor.coadvisor Kyoungtae Lee -
dc.date.awarded 2025-08-01 -
dc.publisher.location Daegu -
dc.description.database dCollection -
dc.citation XT.IM 성97 202508 -
dc.date.accepted 2025-07-21 -
dc.contributor.alternativeDepartment 전기전자컴퓨터공학과 -
dc.subject.keyword SAR ADC, pipelined SAR, loop-unrolled architecture, comparator calibration, wireline communication -
dc.contributor.affiliatedAuthor Heewon Sung -
dc.contributor.affiliatedAuthor Gain Kim -
dc.contributor.affiliatedAuthor Kyoungtae Lee -
dc.contributor.alternativeName 성희원 -
dc.contributor.alternativeName Gain Kim -
dc.contributor.alternativeName 이경태 -
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