Detail View

Microarchitectural Vulnerabilities of Performance and Energy Efficiency Techniques in Data Center Servers

Citations

WEB OF SCIENCE

Citations

SCOPUS

Metadata Downloads

Title
Microarchitectural Vulnerabilities of Performance and Energy Efficiency Techniques in Data Center Servers
Alternative Title
데이터 센터 서버 내 성능 및 에너지 효율 기술의 마이크로아키텍처 취약점
DGIST Authors
Hyosang KimDaewon SeoDonghoon Shin
Advisor
서대원
Co-Advisor(s)
Donghoon Shin
Issued Date
2026
Awarded Date
2026-08-01
Type
Thesis
Description
Microarchitectural Security, Idle states, Accelerator, Covert Channel, Side-channel|마이크로아키텍처 보안, 유휴 상태, 가속기, 은닉 채널, 부채널
Table Of Contents
I. Introduction 1
1.1 Contributions 2
1.2 Organization 3
II. Background 4
2.1 Idle State Management 4
2.2 Network Packet Processing 5
2.3 Intel Data Streaming Accelerator 6
2.4 Covert and Side-channels 7
III. Related Work 8
3.1 Cache-Based Channels 8
3.2 Power-Based Channels 9
3.3 Memory, GPU, and FPGA-Based Channels 11
3.4 On-chip Accelerator-Based Channels 11
IV. BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States 12
4.1 C-states Analysis 12
4.1.1 Wake-up Latency of Core C-states 12
4.1.2 Impact of Core C-states on Request Processing 13
4.2 Threat Model 15
4.3 Covert Channel 16
4.3.1 Mechanism 16
4.3.2 Methodology 18
4.3.3 Evaluation Results 20
4.4 Side-channel: Inferring Keystroke Activities 23
4.4.1 Mechanism 23
4.4.2 Methodology 24
4.4.3 Evaluation Results 25
4.5 Mitigation Strategies for C-state vulnerabilities 26
4.6 Summary 27
V. DarkStream: Exploiting Internal Throughput Contention in Data Streaming Accelerator for Timing Attacks 29
5.1 Internal Contention in DSA 29
5.2 Covert Channel exploiting Intel DSA 32
5.2.1 Threat Model 32
5.2.2 Characterization of Timing Variability Across Operations 33
5.2.3 Analysis of Memory Move as a Covert Channel Primitive 34
5.2.4 DarkStream Covert Channel 35
5.2.5 Methodology 36
5.2.6 Experimental Results 37
5.3 Side-channel 41
5.3.1 Threat Model 42
5.3.2 Approach 42
5.3.3 Website Fingerprinting 47
5.3.4 Deep Learning Model Fingerprinting 49
5.4 Countermeasures 50
5.5 Summary 51
VI. Conclusion 53
References 55
요약문 62
URI
https://scholar.dgist.ac.kr/handle/20.500.11750/60748
http://dgist.dcollection.net/common/orgView/200001006857
DOI
10.22677/THESIS.200001006857
Degree
Doctor
Department
Department of Electrical Engineering and Computer Science
Publisher
DGIST
Show Full Item Record

File Downloads

  • There are no files associated with this item.

공유

qrcode
공유하기

Total Views & Downloads

???jsp.display-item.statistics.view???: , ???jsp.display-item.statistics.download???: