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dc.contributor.author 배진욱 ko
dc.contributor.author 김한별 ko
dc.contributor.author 임준수 ko
dc.contributor.author 이성진 ko
dc.date.accessioned 2019-05-09T07:05:38Z -
dc.date.available 2019-05-09T07:05:38Z -
dc.date.created 2019-05-09 -
dc.date.issued 2019-04 -
dc.identifier.citation 대한임베디드공학회논문지, v.14, no.2, pp.71 - 78 -
dc.identifier.issn 1975-5066 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/9830 -
dc.description.abstract As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL. -
dc.language Korean -
dc.publisher 대한임베디드공학회 -
dc.title 대용량 SSD를 위한 요구 기반 FTL 캐시 분리 기법 -
dc.title.alternative Demand-based FTL Cache Partitioning for Large Capacity SSDs -
dc.type Article -
dc.identifier.doi 10.14372/IEMEK.2019.14.2.71 -
dc.type.local Article(Domestic) -
dc.type.rims ART -
dc.description.journalClass 2 -
dc.identifier.kciid ART002462973 -
dc.identifier.citationVolume 14 -
dc.identifier.citationNumber 2 -
dc.identifier.citationStartPage 71 -
dc.identifier.citationEndPage 78 -
dc.identifier.citationTitle 대한임베디드공학회논문지 -
dc.description.isOpenAccess N -
dc.subject.keywordAuthor DFTL -
dc.subject.keywordAuthor Address translation -
dc.subject.keywordAuthor Cache partitioning -
dc.subject.keywordAuthor Tail latency -
dc.subject.keywordAuthor Write amplification -
dc.contributor.affiliatedAuthor 이성진 -
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Department of Electrical Engineering and Computer Science Data-Intensive Computing Systems Laboratory 1. Journal Articles

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