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Showing results 1 to 6 of 6

Issue Date	Title Author(s) Journal	View
2022-03	A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding Yoon, Jong-Hyeok ; Chang, Muya ; Khwa, Win-San ; Chih, Yu-Der ; Chang, Meng-Fan ; Raychowdhury, Arijit IEEE Journal of Solid-State Circuits, v.57, no.3, pp.845 - 857, 2022-03	162
2022-07	A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores Kim, Minjae ; Kim, Bryan S. ; Lee, Eunji ; Lee, Sungjin IEEE Computer Architecture Letters, v.21, no.2, pp.81 - 84, 2022-07	119
2021-01	Deep Partitioned Training from Near-Storage Computing to DNN Accelerators Jang, Yongjoo ; Kim, Sejin ; Kim, Daehoon ; Lee, Sungjin ; Kung, Jaeha Institute of Electrical and Electronics Engineers, 2021-01	441
2020-09	Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache Jang, Minwoo ; Lee, Seungkyu ; Kung, Jaeha ; Kim, Daehoon IEEE Access, v.8, pp.179837 - 179844, 2020-09	713
2019-07	Exploiting OS-level Memory Offlining for DRAM Power Management Lee, Seung. Hak. ; Kim, N.S. ; Kim, Daehoon IEEE Computer Architecture Letters, v.18, no.2, pp.141 - 144, 2019-07	619
2021-01	IDIO: Orchestrating Inbound Network Data on Server Processors Alian, Mohammad ; Shin, Jongmin ; Kang, Ki Dong ; Wang, Ren ; Daglis, Alexandros ; Kim, Daehoon ; Kim, Nam Sung IEEE Computer Architecture Letters, v.20, no.1, pp.30 - 33, 2021-01	493

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