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전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하

Showing results 1 to 7 of 7

Article
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
  • Yoon, Jong-Hyeok ; 
  • Chang, Muya ; 
  • Khwa, Win-San ; 
  • Chih, Yu-Der ; 
  • Chang, Meng-Fan ; 
  • Raychowdhury, Arijit
  • 2022-03
  • Yoon, Jong-Hyeok. (2022-03). A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE Journal of Solid-State Circuits, 57(3), 845–857. doi: 10.1109/JSSC.2022.3141370
  • Institute of Electrical and Electronics Engineers
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Article
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores
  • Kim, Minjae ; 
  • Kim, Bryan S. ; 
  • Lee, Eunji ; 
  • Lee, Sungjin
  • 2022-07
  • Kim, Minjae. (2022-07). A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores. IEEE Computer Architecture Letters, 21(2), 81–84. doi: 10.1109/LCA.2022.3197654
  • Institute of Electrical and Electronics Engineers
  • View : 354
  • Download : 0
Article
A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture
  • Jung, Sangwoo ; 
  • Lee, Jaehyun ; 
  • Park, Dahoon ; 
  • Lee, Youngjoo ; 
  • Yoon, Jong-Hyeok ; 
  • Kung, Jaeha
  • 2024-12
  • Jung, Sangwoo. (2024-12). A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(12), 5546–5559. doi: 10.1109/TCSI.2024.3395842
  • Institute of Electrical and Electronics Engineers
  • View : 191
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Article
Deep Partitioned Training from Near-Storage Computing to DNN Accelerators
  • 2021-01
  • Jang, Yongjoo. (2021-01). Deep Partitioned Training from Near-Storage Computing to DNN Accelerators. doi: 10.1109/LCA.2021.3081752
  • Institute of Electrical and Electronics Engineers
  • View : 624
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Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache

Article
Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache
  • 2020-09
  • Jang, Minwoo. (2020-09). Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache. IEEE Access, 8, 179837–179844. doi: 10.1109/ACCESS.2020.3027946
  • Institute of Electrical and Electronics Engineers Inc.
  • View : 917
  • Download : 711
Article
Exploiting OS-level Memory Offlining for DRAM Power Management
  • 2019-07
  • Lee, Seung. Hak. (2019-07). Exploiting OS-level Memory Offlining for DRAM Power Management. IEEE Computer Architecture Letters, 18(2), 141–144. doi: 10.1109/LCA.2019.2942914
  • Institute of Electrical and Electronics Engineers
  • View : 781
  • Download : 0
Article
IDIO: Orchestrating Inbound Network Data on Server Processors
  • Alian, Mohammad ; 
  • Shin, Jongmin ; 
  • Kang, Ki Dong ; 
  • Wang, Ren ; 
  • Daglis, Alexandros ; 
  • Kim, Daehoon ; 
  • Kim, Nam Sung
  • 2021-01
  • Alian, Mohammad. (2021-01). IDIO: Orchestrating Inbound Network Data on Server Processors. IEEE Computer Architecture Letters, 20(1), 30–33. doi: 10.1109/lca.2020.3044923
  • Institute of Electrical and Electronics Engineers
  • View : 690
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