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Exploiting OS-level Memory Offlining for DRAM Power Management
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Title
Exploiting OS-level Memory Offlining for DRAM Power Management
Issued Date
2019-07
Citation
Lee, Seung. Hak. (2019-07). Exploiting OS-level Memory Offlining for DRAM Power Management. IEEE Computer Architecture Letters, 18(2), 141–144. doi: 10.1109/LCA.2019.2942914
Type
Article
Author Keywords
Random access memoryMemory managementEnergy consumptionHardwareSoftwareLinuxDRAMmemory offliningpower management
Keywords
Computer hardwareComputer operating systemsComputer softwareEnergy utilizationLinuxPower managementand Daehoon KimMemory managementNam Sung KimRandom access memorySeunghak LeeDynamic random access storage
ISSN
1556-6056
Abstract
Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, background power accounts for a considerable fraction of the total DRAM power consumption; the fraction will increase further in the near future, especially when slowing-down technology scaling forces us to provide necessary DRAM capacity through plugging in more DRAM modules or stacking more DRAM chips in a DRAM package. Although current DRAM architecture supports low power states at rank granularity that turn off some components during idle periods, techniques to exploit memory-level parallelism make the rank-granularity power state become ineffective. Furthermore, the long wake-up latency is one of obstacles to adopting aggressive power management (PM) with deep power-down states. By tackling the limitations, we propose OffDIMM that is a software-assisted DRAM PM collaborating with the OS-level memory onlining/offlining. OffDIMM maps a memory block in the address space of the OS to a subarray group or groups of DRAM, and sets a deep power-down state for the subarray group when offlining the block. Through the dynamic OS-level memory onlining/offlining based on the current memory usage, our experimental results show OffDIMM reduces background power by 24 percent on average without notable performance overheads. © 2002-2011 IEEE.
URI
http://hdl.handle.net/20.500.11750/10987
DOI
10.1109/LCA.2019.2942914
Publisher
Institute of Electrical and Electronics Engineers
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김대훈
Kim, Daehoon김대훈

Department of Electrical Engineering and Computer Science

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