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Exploiting OS-level Memory Offlining for DRAM Power Management
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dc.contributor.author Lee, Seung. Hak. -
dc.contributor.author Kim, N.S. -
dc.contributor.author Kim, Daehoon -
dc.date.accessioned 2019-12-16T01:02:49Z -
dc.date.available 2019-12-16T01:02:49Z -
dc.date.created 2019-10-10 -
dc.date.issued 2019-07 -
dc.identifier.issn 1556-6056 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/10987 -
dc.description.abstract Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, background power accounts for a considerable fraction of the total DRAM power consumption; the fraction will increase further in the near future, especially when slowing-down technology scaling forces us to provide necessary DRAM capacity through plugging in more DRAM modules or stacking more DRAM chips in a DRAM package. Although current DRAM architecture supports low power states at rank granularity that turn off some components during idle periods, techniques to exploit memory-level parallelism make the rank-granularity power state become ineffective. Furthermore, the long wake-up latency is one of obstacles to adopting aggressive power management (PM) with deep power-down states. By tackling the limitations, we propose OffDIMM that is a software-assisted DRAM PM collaborating with the OS-level memory onlining/offlining. OffDIMM maps a memory block in the address space of the OS to a subarray group or groups of DRAM, and sets a deep power-down state for the subarray group when offlining the block. Through the dynamic OS-level memory onlining/offlining based on the current memory usage, our experimental results show OffDIMM reduces background power by 24 percent on average without notable performance overheads. © 2002-2011 IEEE. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title Exploiting OS-level Memory Offlining for DRAM Power Management -
dc.type Article -
dc.identifier.doi 10.1109/LCA.2019.2942914 -
dc.identifier.wosid 000505542500006 -
dc.identifier.scopusid 2-s2.0-85072722741 -
dc.identifier.bibliographicCitation Lee, Seung. Hak. (2019-07). Exploiting OS-level Memory Offlining for DRAM Power Management. IEEE Computer Architecture Letters, 18(2), 141–144. doi: 10.1109/LCA.2019.2942914 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Random access memory -
dc.subject.keywordAuthor Memory management -
dc.subject.keywordAuthor Energy consumption -
dc.subject.keywordAuthor Hardware -
dc.subject.keywordAuthor Software -
dc.subject.keywordAuthor Linux -
dc.subject.keywordAuthor DRAM -
dc.subject.keywordAuthor memory offlining -
dc.subject.keywordAuthor power management -
dc.subject.keywordPlus Computer hardware -
dc.subject.keywordPlus Computer operating systems -
dc.subject.keywordPlus Computer software -
dc.subject.keywordPlus Energy utilization -
dc.subject.keywordPlus Linux -
dc.subject.keywordPlus Power management -
dc.subject.keywordPlus and Daehoon Kim -
dc.subject.keywordPlus Memory management -
dc.subject.keywordPlus Nam Sung Kim -
dc.subject.keywordPlus Random access memory -
dc.subject.keywordPlus Seunghak Lee -
dc.subject.keywordPlus Dynamic random access storage -
dc.citation.endPage 144 -
dc.citation.number 2 -
dc.citation.startPage 141 -
dc.citation.title IEEE Computer Architecture Letters -
dc.citation.volume 18 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Computer Science -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture -
dc.type.docType Article -
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김대훈
Kim, Daehoon김대훈

Department of Electrical Engineering and Computer Science

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