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dc.contributor.advisor 이종수 -
dc.contributor.author Hyun-Soo Ra -
dc.date.accessioned 2019-08-22T16:01:10Z -
dc.date.available 2019-08-22T16:01:10Z -
dc.date.issued 2019 -
dc.identifier.uri http://dgist.dcollection.net/common/orgView/200000219559 en_US
dc.identifier.uri http://hdl.handle.net/20.500.11750/10469 -
dc.description Low Dimensional materials, 2D materials, 0D materials, Hybrid, Optoelectronics, Hetrojunction -
dc.description.statementofresponsibility prohibition -
dc.description.tableofcontents 1. Introduction
1 Basic Theory of Low Dimensional Materials 1
1.1 Emerging 2 Dimensional Materials 3
1.2 Emerging 0 Dimensional Materials 5
1.3 Device Fabrication Technology 7
1.4 Hybrid Structure with 2D-0D and 2D-2D 10
1.4.1 Exiton generation (absorption coefficient) 11
1.4.2 Exiton separation to free charge carrier 12
1.4.3 Electrical and optical trap issue 14
1.4.4 High mobility for harvesting free charge 18
1.5 Transistor and Phototransistor 19
1.6 p-n junction photodiode 23
1.7 Optoelectronics characterization 24
1.7.1 Field effect transistor (FET) characteristics 24
1.7.2 Photodetector characteristics 25
References 31
2. Hybrid MoS2 nanosheet-CdSe nanocrystals phototransistor with fast photoresponse
2.1 Introduction 42
2.2 Research direction 42
2.3 Experimental 43
2.3.1 Device fabrication 43
2.3.2 Synthesis of colloidal CdSe nanocrystals 43
2.3.3 Raman and photoluminescence spectroscopy 44
2.3.4 Photoresponse measurement system and setup 44
2.3.5 Work-function calculation using density function theory (DFT) 44
2.4. Results and discussion 45
2.4.1 MoS2 field effect transistor fabrication and spectroscopy analysis 46
2.4.2 CdSe NCs characteristics and deposition method 46
2.4.3 Comparison of phototransistor characteristics 47
2.4.4 Measuring and calculating figure of merits in hybrid phototransistors 51
2.4.5 Photoresponse time analysis and operation mechanism using band-alignment 53
2.4.6 Summary and comparison with literatures 54
2.4.7 Band energy location approach method 55
2.5. Conclusions 58
2.6. References 59
3. Dual-gate black phosphorus field-effect transistors with hexagonal boron nitride
as dielectric and passivation layer
3.1 Introduction 64
3.2 Experimental section 65
3.2.1 Surface modeling of Black phosphorus with dielectric layer 65
3.2.2 2D Materials Information and sampling preparation 65
3.2.3 Device Fabrication and measurement setup 65
3.2.4 AFM and Raman Spectroscopy condition 67
3.3 Results and discussion 68
3.3.1 Surface modeling and capacitance analysis 68
3.3.2 Architecture of field effect transistor (FET) and fabrication 70
3.3.3 Electrical properties of black phosphorus FET 72
3.3.4 Annealing effect of black phosphorus FET 73
3.3.5 Schottky barrier study 74
3.3.6 High mobility device 75
3.3.7 Gate leakage comparison via SiO2 and h-BN 76
3.3.8 Architecture analysis using cross sectional TEM 77
3.3.9 Device modeling and band alignment 78
3.3.10 Device reliability 79
3.3.11 Graphene and MoS2 architecture study 81
3.3.12 Black phosphorus passivation history 83
3.4 Conclusions 84
3.5 References 85
4. Photocurrent and Noise Origin in Van der Waals Heterojunction
4.1 Introduction 92
4.2 Experimental section 94
4.2.1 Device fabrication 94
4.2.2 Electrical and scanning photocurrent mapping measurement 94
4.2.3 Noise measurement 95
4.2.4 Raman and AFM characteristics 95
4.3 2D heterojunction device design 95
4.3.1 Used 2D thickness measurement using AFM 98
4.4 Optoelectronic properties 100
4.4.1 WSe2 annealing to enhance p-type property 100
4.4.2 Hole enhancement of WSe2 through annealing process 101
4.4.3 Tunable carrier (electron) concentration of WS2 as a function of a gate bias 101
4.4.4 The p-n junction photovoltaic effect analysis 105
4.5 Scanning photocurrent mapping 107
4.5.1 Laser beam size for scanning photocurrent mapping 107
4.5.2 different diode characteristics 109
4.5.3 Depletion width as a function of charge balance 110
4.5.4 Tunneling leakage current effect 114
4.5.5 Transistor application like quasi p-n-p 115
4.6 Noise analysis and Detectivity 115
4.6.1 Noise composition 115
4.6.2 Electrical hysteresis of diode transient gate region 119
4.6.3 Time-Resolved Photocurrent Response at p-n and n-n junction 121
4.6.4 TRPR from the perspective of junction capacitance 122
4.7 Conclusion 124
4.8 References 125
5. 요약문 129
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dc.format.extent 149 -
dc.language eng -
dc.publisher DGIST -
dc.source /home/dspace/dspace53/upload/200000219559.pdf -
dc.subject 광전나노소자 -
dc.title Low-Dimensional Semiconductor Hybrid Device for Optoelectronics Application -
dc.title.alternative Low-Dimensional Semiconductor Hybrid Device for Optoelectronics Application -
dc.type Thesis -
dc.identifier.doi 10.22677/thesis.200000219559 -
dc.description.degree Doctor -
dc.contributor.department Department of Energy Science and Engineering -
dc.contributor.coadvisor Jae Dong Lee -
dc.date.awarded 2019-08 -
dc.publisher.location Daegu -
dc.description.database dCollection -
dc.citation XT.ED 나94 201908 -
dc.date.accepted 2019-07-01 -
dc.contributor.alternativeDepartment 에너지공학전공 -
dc.embargo.liftdate 2021-08-25 -
dc.contributor.affiliatedAuthor Lee, JaeDong -
dc.contributor.affiliatedAuthor Ra, Hyun-Soo -
dc.contributor.affiliatedAuthor Lee, Jong-Soo -
dc.contributor.alternativeName 이재동 -
dc.contributor.alternativeName 나현수 -
dc.contributor.alternativeName Jong-Soo Lee -
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