Cd3As2, Dirac semimetal, p-n junction, quantum transport
Dirac semimetals such as Cd3As2 have drawn significant interest owing to their distinctive linear band structure. Several studies investigate the intriguing physical phenomena and electronic properties of these materials. In this study, Cd3As2 nanowires were synthesized using vapor transport method and transferred to a highly doped p-silicon substrate where recessed bottom gates were initially fabricated. Tuning of the bottom gates resulted to the realization of four conductance regimes forming p-n junctions in the nanowire device. Measurements at high magnetic fields show the formation of quantum dot in the bipolar regime. We find that the electrostatic potentials by the bottom gates as well as the suppression of Klein tunneling by magnetic field serves as tunnel barriers for the quantum confinement. Further investigation by performing both two-terminal and four-terminal measurements, allows the determination of contact resistance as well as electron and hole mobility. The ease in tunability of Cd3As2 makes it a practical candidate for functional quantum devices that require precise control of carrier density.
Table Of Contents
1. Theoretical Background 1 1.1 Dirac Semimetal 1 1.2 Cadmium Arsenide (Cd3As2) 3 1.3 p-n Junctions in Dirac Semimetal 4 1.4 Quantum Dot 6 1.5 Motivation and Potential Application 9 2. Suspended Nanowire Device Fabrication 10 2.1 Nanowire Growth 10 2.2 Bottom Gate Fabrication 11 2.3 Nanowire Transfer 12 2.4 Device Fabrication 13 3. Measurement Techniques 15 3.1 Initial Characterization and Sample Preparation 15 3.2 Measurement Schematic 17 3.3 Low Temperature Measurement Setup 17 3.4 He-3 Refrigeration System 19 4. Experimental Results 21 4.1 Device Specifications 21 4.2 p-n Junctions in Cd3As2 Nanostructures 22 4.3 Quantum Dot Formation 27 4.4 Suspended vs Non suspended structure 29 4.5 Contact Resistance Measurement 30 4.6 Fabry Perot Interference 31 4.7 Mobility by Four Terminal Measurement 33 5. Summary and Conclusion 35 Bibliography 36 Appendix 41 A. Fabrication Details and Recipes 41 A.1 Wafer Characteristics 41 A.2 Photopad Fabrication 41 A.3 Designing using KLayout and Layout Editor 42 A.4 Bottom Gate Fabrication 44 A.5 Device Fabrication 45 B. Pre Cooldown Sample Preparation 46 B.1 Wirebonding 46 B.2 He-3 Sample Exchange Procedure (Unloading and loading Sample) 47 Korean Summary 48 Acknowledgements 49