Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Alian, Mohammad | - |
dc.contributor.author | Shin, Jongmin | - |
dc.contributor.author | Kang, Ki Dong | - |
dc.contributor.author | Wang, Ren | - |
dc.contributor.author | Daglis, Alexandros | - |
dc.contributor.author | Kim, Daehoon | - |
dc.contributor.author | Kim, Nam Sung | - |
dc.date.accessioned | 2021-01-22T06:58:41Z | - |
dc.date.available | 2021-01-22T06:58:41Z | - |
dc.date.created | 2021-01-04 | - |
dc.date.issued | 2021-01 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/12636 | - |
dc.description.abstract | Network bandwidth demand in datacenters is doubling every 12 to 15 months. In response to this demand, high-bandwidth network interface cards, each capable of transferring 100s of Gigabits of data per second, are making inroads into the servers of next-generation datacenters. Such unprecedented data delivery rates on server endpoints raise new challenges, as inbound network traffic placement decisions within the memory hierarchy have a direct impact on end-to-end performance. Modern server-class Intel processors leverage DDIO technology to steer all inbound network data into the last-level cache (LLC), regardless of the network traffic's nature. This static data placement policy is suboptimal, both from a performance and an energy efficiency standpoint. In this work, we design IDIO, a framework that-unlike DDIO-dynamically decides where to place inbound network traffic within a server's multi-level memory hierarchy. IDIO dynamically monitors system behavior and distinguishes between different traffic classes to determine and periodically re-evaluate the best placement location for each flow: LLC, mid-level (L2) cache or DRAM. Our results show that IDIO increases a server's maximum sustainable load by up to ˜33.3% across various network functions. IEEE | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | IDIO: Orchestrating Inbound Network Data on Server Processors | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/lca.2020.3044923 | - |
dc.identifier.scopusid | 2-s2.0-85098773402 | - |
dc.identifier.bibliographicCitation | IEEE Computer Architecture Letters, v.20, no.1, pp.30 - 33 | - |
dc.description.isOpenAccess | FALSE | - |
dc.subject.keywordAuthor | Cache | - |
dc.subject.keywordAuthor | Network | - |
dc.subject.keywordAuthor | Data Direct I/O | - |
dc.subject.keywordAuthor | Datacenters | - |
dc.subject.keywordPlus | Bandwidth | - |
dc.subject.keywordPlus | Random access memory | - |
dc.subject.keywordPlus | Servers | - |
dc.subject.keywordPlus | Interference | - |
dc.subject.keywordPlus | Program processors | - |
dc.subject.keywordPlus | Noise measurement | - |
dc.subject.keywordPlus | Performance evaluation | - |
dc.citation.endPage | 33 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 30 | - |
dc.citation.title | IEEE Computer Architecture Letters | - |
dc.citation.volume | 20 | - |
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