An Antiphase-synchronized Dual Ring Oscillator Based Capacitive Voltage Doubler with Power Optimizable Feedback Loop

Abstract

This thesis proposed an antiphase-synchronized dual ring oscillator based voltage doubler with power optimizable feedback loop. This voltage doubler is suitable for wearable IoT devices that use battery power in terms of power efficiency and area. The antiphase-synchronization with two ring oscillator makes the output voltage ripple smaller which is inevitable in ring oscillator based voltage doubler due to its phase mismatch. Minimizing such ripple can reduce energy and area consumption by eliminating the need for an additional ripple reduction circuit. Besides, the power efficiency will be optimized by the digital feedback loop. It detects the output voltage and tunes the frequency according to the equation about the relationship between the output voltage and power efficiency. This chip is fabricated in the 180nm CMOS process and occupies 0.086$\text{mm}^2$. It achieves 79\% power efficiency within the load current 35 - 90 $\mu A$. It is not the best power efficiency compared to other state-of-the-art circuits. However, it is not suitable for a one-to-one comparison with other circuits that needs external blocks such as LDO for ripple reduction, clock, and supply voltage for the feedback loop.