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CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads

Title
CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads
Author(s)
Park, GyeongseoKang, Ki-DongKim, MinhoKim, Daehoon
Issued Date
2023-01
Citation
IEEE Computer Architecture Letters, v.22, no.1, pp.1 - 4
Type
Article
Author Keywords
Dynamic core allocationenergy efficiencyprocessor idle state
ISSN
1556-6056
Abstract
In data-center servers, the dynamic core allocation for Latency-Critical (LC) applications can play a crucial role in improving energy efficiency under Service Level Objective (SLO) constraints, allowing cores to enter idle states (i.e., C-states) that consume less power by turning off a part of hardware components of a processor. However, prior studies focus on the core allocation for application threads while not considering cores involved in network packet processing, even though packet processing affects not only response latency but also energy consumption considerably. In this paper, we first investigate the impacts of the explicit core allocation for network packet processing on the tail response latency and energy consumption while running LC applications. We observe that co-adjusting the number of cores for network packet processing along with the number of cores for LC application threads can improve energy efficiency substantially, compared with adjusting the number of cores only for application threads, as prior studies do. In addition, we propose a dynamic core allocation, called CoreNap, which allocates/de-allocates cores for both LC application threads and packet processing. CoreNap measures the CPU-utilization by application threads and packet processing individually, and predicts response latency and power consumption when the combination of core allocation is enforced via a lightweight prediction model. Based on the prediction, CoreNap chooses/enforces the energy-efficient combination of core allocation. Our experimental results show that CoreNap reduces energy consumption by up to 18.6% compared with state-of-the-art study that adjusts cores only for LC application in parallel packet processing environments. IEEE
URI
http://hdl.handle.net/20.500.11750/17490
DOI
10.1109/LCA.2022.3227629
Publisher
Institute of Electrical and Electronics Engineers
Related Researcher
  • 김대훈 Kim, Daehoon
  • Research Interests Computer Architecture and Systems; Virtualization; Cloud Computing
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Department of Electrical Engineering and Computer Science Computer Architecture and Systems Lab 1. Journal Articles

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