Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yonar, A. Serdar | - |
dc.contributor.author | Francese, Pier Andrea | - |
dc.contributor.author | Brandli, Matthias | - |
dc.contributor.author | Kossel, Marcel | - |
dc.contributor.author | Prathapan, Mridula | - |
dc.contributor.author | Morf, Thomas | - |
dc.contributor.author | Ruffino, Andrea | - |
dc.contributor.author | Kim, Gain | - |
dc.contributor.author | Jang, Taekwang | - |
dc.date.accessioned | 2023-10-23T18:40:23Z | - |
dc.date.available | 2023-10-23T18:40:23Z | - |
dc.date.created | 2023-07-20 | - |
dc.date.issued | 2023-07 | - |
dc.identifier.issn | 2573-9603 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/46548 | - |
dc.description.abstract | An 8-bit digital intensive time-based ADC implemented in 5-nm CMOS is presented in this letter. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75 Vpp,diff. A redundancy scheme for the input polarity decision taken for 1-bit voltage domain folding is introduced against wrong decisions which eliminates comparator calibration in analog domain and allows a more efficient design. Sense amplifier latch (SAL) interpolation technique is presented which reduces the power and area consumption when phase interpolating the time-to-digital converter (TDC) signals. The ADC reaches 1 GS/s sampling rate with 0.7-V supply and 1.25 GS/s with 0.8-V supply and achieves 16.6 and 20.3 fJ/conv-step Walden FoM, respectively. The total active area is 313μ m2. © IEEE. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | An 8b 1.0-to-1.25GS/s Time-Based ADC with Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LSSC.2023.3293273 | - |
dc.identifier.scopusid | 2-s2.0-85164405567 | - |
dc.identifier.bibliographicCitation | IEEE Solid-State Circuits Letters, v.6, pp.196 - 196 | - |
dc.description.isOpenAccess | TRUE | - |
dc.subject.keywordAuthor | Time-based ADC | - |
dc.subject.keywordAuthor | voltage-to-time converter | - |
dc.subject.keywordAuthor | time-to-digital converter | - |
dc.subject.keywordAuthor | phase interpolation | - |
dc.subject.keywordAuthor | redundancy | - |
dc.subject.keywordAuthor | ringoscillator | - |
dc.citation.endPage | 196 | - |
dc.citation.startPage | 196 | - |
dc.citation.title | IEEE Solid-State Circuits Letters | - |
dc.citation.volume | 6 | - |
There are no files associated with this item.