Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Lee, Myungguk | - |
dc.contributor.author | Cho, Jaeik | - |
dc.contributor.author | Choi, Junung | - |
dc.contributor.author | Choi, Won Joon | - |
dc.contributor.author | Lee, Jiyun | - |
dc.contributor.author | Jang, Iksu | - |
dc.contributor.author | Moon, Changjae | - |
dc.contributor.author | Kim, Gain | - |
dc.contributor.author | Kim, Byungsub | - |
dc.date.accessioned | 2024-01-03T21:40:12Z | - |
dc.date.available | 2024-01-03T21:40:12Z | - |
dc.date.created | 2023-12-18 | - |
dc.date.issued | 2024-01 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/47532 | - |
dc.description.abstract | This paper presents compact single-ended wireline transceivers with software-generated receiver front-ends. The developed software framework significantly shortens the physical design time of 1/N-rate wireline receiver front-ends. The physical layouts of various receiver front-ends were software-generated in four different CMOS technology nodes (28 nm, 40 nm, 65 nm, and 90 nm) with four different front-end architectures targeting various data rates. In the post-layout simulation, the receiver front-ends generated within a second by the software achieved nearly the same performances as the manually-designed receiver front-ends that require more than about 30 hours of design time. For demonstration, we generated 8 Gb/s full-rate, 10 Gb/s half-rate, 12 Gb/s, and 20 Gb/s quarter-rate receiver front-ends, and fabricated them with a manually-designed feed-forward equalization transmitter in 28 nm CMOS process. The transceivers were measured with the data rate up to 20 Gb/s while consuming 1.39 pJ/b at the channel loss of |
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dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSI.2023.3332391 | - |
dc.identifier.wosid | 001122841800001 | - |
dc.identifier.scopusid | 2-s2.0-85178076306 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems I: Regular Papers, v.71, no.1, pp.373 - 382 | - |
dc.description.isOpenAccess | FALSE | - |
dc.subject.keywordAuthor | short-reach links | - |
dc.subject.keywordAuthor | single-ended signaling | - |
dc.subject.keywordAuthor | layout design automation | - |
dc.subject.keywordAuthor | analog layout generator | - |
dc.subject.keywordAuthor | receiver front-end generator | - |
dc.subject.keywordAuthor | Wireline communications | - |
dc.citation.endPage | 382 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 373 | - |
dc.citation.title | IEEE Transactions on Circuits and Systems I: Regular Papers | - |
dc.citation.volume | 71 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.type.docType | Article | - |
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