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dc.contributor.author Choi, Hanho -
dc.contributor.author Song, Ha-Il -
dc.contributor.author Won, Hyosup -
dc.contributor.author Yoo, Junyoung -
dc.contributor.author Kwon, Woohyun -
dc.contributor.author Jin, Huxian -
dc.contributor.author Kwon, Konan -
dc.contributor.author Lee, Cheongmin -
dc.contributor.author Kim, Gain -
dc.contributor.author Eu, Jake -
dc.contributor.author Park, Sean -
dc.contributor.author Bae, Hyeon-Min -
dc.date.accessioned 2024-01-19T00:10:42Z -
dc.date.available 2024-01-19T00:10:42Z -
dc.date.created 2023-11-16 -
dc.date.issued 2023-09-13 -
dc.identifier.isbn 9798350304206 -
dc.identifier.issn 2643-1319 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/47628 -
dc.description.abstract This paper presents an 86. 71875GHz R transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop for waveguide links. The IC fabricated in 28nm CMOS demonstrates 57. 8125Gb/s PAM-4 data transmission over a 1. 5m waveguide channel. The proposed carrier synchronization can be achieved only by using a base-band CDR without using power-and-area-hungry RF circuits. The test chip achieves the best figure of merit (FoM) of 3. 5pJ/b/m in terms of throughput-distance, and energy efficiency compared to the prior art. © 2023 IEEE. -
dc.language English -
dc.publisher IEEE Solid-State Circuits Society -
dc.title An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm -
dc.type Conference Paper -
dc.identifier.doi 10.1109/ESSCIRC59616.2023.10268802 -
dc.identifier.scopusid 2-s2.0-85175240342 -
dc.identifier.bibliographicCitation European Solid-State Circuits Conference, pp.181 - 184 -
dc.identifier.url https://epapers2.org/ess2023/ESR/paper_details.php?paper_id=9369 -
dc.citation.conferencePlace PO -
dc.citation.conferencePlace Lisbon -
dc.citation.endPage 184 -
dc.citation.startPage 181 -
dc.citation.title European Solid-State Circuits Conference -
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Department of Electrical Engineering and Computer Science Circuits And Systems for Signal Processing (CASSP) Laboratory 2. Conference Papers

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