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dc.contributor.author Chen, Hanning -
dc.contributor.author Kim, Yeseong -
dc.contributor.author Sadredini, Elaheh -
dc.contributor.author Gupta, Saransh -
dc.contributor.author Latapie, Hugo -
dc.contributor.author Imani, Mohsen -
dc.date.accessioned 2024-02-08T23:10:12Z -
dc.date.available 2024-02-08T23:10:12Z -
dc.date.created 2024-01-02 -
dc.date.issued 2023-10-16 -
dc.identifier.isbn 9798350325997 -
dc.identifier.issn 2324-8432 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/47907 -
dc.description.abstract In this paper, we propose a Hyper-Dimensional genome analysis platform. Instead of working with original sequences, our method maps the genome sequences into high-dimensional space and performs sequence matching with simple and parallel similarity searches. At the algorithm level, we revisit the sequence searching with brain-like memorization that Hyper-Dimensional computing natively supports. Instead of working on the original data, we map all data points into high-dimensional space, enabling the main sequence searching operations to process in a hardware-friendly way. We accordingly design a density-aware FPGA implementation. Our solution searches the similarity of an encoded query and large-scale genome library through different chunks. We exploit the holographic representation of patterns to stop search operations on libraries with a lower chance of a match. This translates our computation from dense to highly sparse just after a few chuck-based searches. Our evaluation shows that our accelerator can provide 46× speedup and 188× energy efficiency improvement compared to a state-of-the-art GPU implementation. Results show that our accelerator achieves up to 3440.6 GCUPS using a single Xilinx Alveo U280 board. © 2023 IEEE. -
dc.language English -
dc.publisher International Federation for Information Processing Technical Committee -
dc.relation.ispartof IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC -
dc.title Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration -
dc.type Conference Paper -
dc.identifier.doi 10.1109/VLSI-SoC57769.2023.10321874 -
dc.identifier.wosid 001108827200008 -
dc.identifier.scopusid 2-s2.0-85179848318 -
dc.identifier.bibliographicCitation IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, pp.44 - 49 -
dc.identifier.url https://easychair.org/smart-program/VLSI-SoC2023/2023-10-16.html#talk:235290 -
dc.citation.conferenceDate 2023-10-16 -
dc.citation.conferencePlace AR -
dc.citation.conferencePlace Dubai, U ARAB EMIRATES -
dc.citation.endPage 49 -
dc.citation.startPage 44 -
dc.citation.title IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 -
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Department of Electrical Engineering and Computer Science Computation Efficient Learning Lab. 2. Conference Papers

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