Title

HW/SW design to prevent the bit-flip by Row Hammering in DRAM

Alternative Title

DRAM에서의 로우 해머링에 의한 비트 플립을 방지하는 하드웨어 및 소프트웨어 설계

DGIST Authors

Seunghak Lee ; Daehoon Kim ; Jaeha Kung

Advisor

김대훈

Co-Advisor(s)

Jaeha Kung

Issued Date

2024

Awarded Date

2024-02-01

Citation

Seunghak Lee. (2024). HW/SW design to prevent the bit-flip by Row Hammering in DRAM. doi: 10.22677/THESIS.200000723486

Type

Thesis

Description

DRAM;Row Hammering;Integrity;Reliability;Memory Offlining

Table Of Contents

I. Introduction 1
1.1. Contributions 3
1.2. Organization 4
II. Background 5
2.1. DRAM Architecture 5
2.2. Memory Request and DRAM Operation 5
2.3. Row Hammering (RH) 7
2.4. Memory Offlining in modern OS 8
III. Related work 10
3.1. Methodology to bypass the Cache 10
3.2. Existing RH Mitigation Technique 11
3.3. Memory Offlining 13
IV. NoHammer: Preventing Row Hammering with Last-Level Cache Management 15
4.1. Threat Model 15
4.2. Main Architecture 15
4.2.1. Aggressor Rows Tracking 15
4.2.2. Set Associativity Extending 16
4.2.3. LLC Tag matching 18
4.2.4. Cache Replacement Policy 18
4.3. Security Analysis 19
4.4. Case Study 20
4.4.1. Many-sided RH (N-assisted double-sided RH) 21
4.4.2. Distance-2 RH (Half-Double) 22
4.5. Evaluation 23
4.5.1. Experimental Methodology 23
4.5.2. Performance Overheads 25
4.5.3. DRAM Energy Consumption 27
4.5.4. Storage Analysis 28
4.6. Discussion 29
4.7. Summary 30
V. OFF-Hammer: Memory Offlining Based Row Hammering Mitigation 31
5.1. Threat Model 31
5.2. Main Architecture 31
5.2.1. Row Activation Tracker: RAT 32
5.2.2. Address Translation Module: ATM 33
5.2.3. Page Offlining Module: POM 35
5.2.4. Row Copy Engine: RCE 37
5.3. Security Analysis 38
5.4. Case Study 40
5.4.1. Many-sided RH (N-assisted double-sided RH) 41
5.4.2. Distance-2 RH (Half-Double) 42
5.5. Evaluation 43
5.5.1. Experimental Methodology 43
5.5.2. Performance Overheads 46
5.5.3. Storage Analysis 46
5.6. Summary 47
VI. Integrated Row Hammering Mitigation 48
6.1. Description of Integrated Mitigation Model between NoHammer and OFF-Hammer 48
6.2. Performance Evaluation of Integrated NoFF-Hammer 48
VII. Conclusion 51
References 52

URI

http://hdl.handle.net/20.500.11750/48034
http://dgist.dcollection.net/common/orgView/200000723486

DOI

10.22677/THESIS.200000723486

Degree

Doctor

Department

Department of Electrical Engineering and Computer Science

Publisher

DGIST

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