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A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency
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dc.contributor.author Youn, Donghyun -
dc.contributor.author Kim, Youngin -
dc.contributor.author Choi, Injun -
dc.contributor.author Jung, Yoontae -
dc.contributor.author Jeon, Hyuntak -
dc.contributor.author Lee, Kyoungtae -
dc.contributor.author Kweon, Soon-Jae -
dc.contributor.author Ha, Sohmyung -
dc.contributor.author Je, Minkyu -
dc.date.accessioned 2024-10-08T10:40:13Z -
dc.date.available 2024-10-08T10:40:13Z -
dc.date.created 2024-07-19 -
dc.date.issued 2024-07 -
dc.identifier.issn 2169-3536 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/56948 -
dc.description.abstract This paper presents a wide-dynamic-range, DC-coupled, time-based neural-recording integrated circuit (IC), which is resilient against stimulation artifacts, for bidirectional neural interfaces. The proposed neural-recording IC based on delta-sigma modulation consists of an input Gm cell, current-controlled oscillator (CCO)-based integrator, phase quantizer, and tri-level current-steering DACs. The feedback current-steering DACs embedded in the current sources of the input Gm cell enable the recording IC to achieve a wide enough dynamic range to directly digitize the neural signals on top of stimulation artifacts while maintaining a moderately high input impedance. Moreover, the free-running frequency of the CCO-based integrator is set to be the optimum frequency of 0.49 times the sampling rate, thereby achieving high loop gain while utilizing inherent clocked averaging (CLA). Designed and post-layout simulated in a 65-nm process, the neural-recording IC achieves an SNDR of 76.3 dB over a signal bandwidth of 10 kHz while consuming low power of 5.04μ W with a sufficiently wide linear input range of 200 mVPP. © 2024 The Authors. -
dc.language English -
dc.publisher IEEE -
dc.title A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency -
dc.type Article -
dc.identifier.doi 10.1109/ACCESS.2024.3424228 -
dc.identifier.wosid 001272140700001 -
dc.identifier.scopusid 2-s2.0-85197546694 -
dc.identifier.bibliographicCitation Youn, Donghyun. (2024-07). A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency. IEEE Access, 12, 94354–94366. doi: 10.1109/ACCESS.2024.3424228 -
dc.description.isOpenAccess TRUE -
dc.subject.keywordAuthor Bidirectional neural interface -
dc.subject.keywordAuthor current-controlled oscillator (CCO) -
dc.subject.keywordAuthor closed-loop neuromodulation -
dc.subject.keywordAuthor linear input range -
dc.subject.keywordAuthor neural recording -
dc.subject.keywordAuthor optimization -
dc.subject.keywordAuthor time-based delta-sigma modulator (DSM) -
dc.subject.keywordAuthor wide dynamic range -
dc.subject.keywordPlus SYSTEM -
dc.subject.keywordPlus FRONT-END -
dc.subject.keywordPlus LOOP -
dc.subject.keywordPlus STIMULATION -
dc.subject.keywordPlus INTEGRATOR -
dc.subject.keywordPlus AMPLIFIER -
dc.subject.keywordPlus DAC -
dc.subject.keywordPlus AFE -
dc.subject.keywordPlus INTERFACE -
dc.citation.endPage 94366 -
dc.citation.startPage 94354 -
dc.citation.title IEEE Access -
dc.citation.volume 12 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Computer Science; Engineering; Telecommunications -
dc.relation.journalWebOfScienceCategory Computer Science, Information Systems; Engineering, Electrical & Electronic; Telecommunications -
dc.type.docType Article -
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