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Department of Electrical Engineering and Computer Science
Sensor Systems and Circuits Laboratory
1. Journal Articles
A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency
Youn, Donghyun
;
Kim, Youngin
;
Choi, Injun
;
Jung, Yoontae
;
Jeon, Hyuntak
;
Lee, Kyoungtae
;
Kweon, Soon-Jae
;
Ha, Sohmyung
;
Je, Minkyu
Department of Electrical Engineering and Computer Science
Sensor Systems and Circuits Laboratory
1. Journal Articles
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Title
A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency
Issued Date
2024-07
Citation
Youn, Donghyun. (2024-07). A Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC with Optimized CCO Frequency. IEEE Access, 12, 94354–94366. doi: 10.1109/ACCESS.2024.3424228
Type
Article
Author Keywords
Bidirectional neural interface
;
current-controlled oscillator (CCO)
;
closed-loop neuromodulation
;
linear input range
;
neural recording
;
optimization
;
time-based delta-sigma modulator (DSM)
;
wide dynamic range
Keywords
SYSTEM
;
FRONT-END
;
LOOP
;
STIMULATION
;
INTEGRATOR
;
AMPLIFIER
;
DAC
;
AFE
;
INTERFACE
ISSN
2169-3536
Abstract
This paper presents a wide-dynamic-range, DC-coupled, time-based neural-recording integrated circuit (IC), which is resilient against stimulation artifacts, for bidirectional neural interfaces. The proposed neural-recording IC based on delta-sigma modulation consists of an input Gm cell, current-controlled oscillator (CCO)-based integrator, phase quantizer, and tri-level current-steering DACs. The feedback current-steering DACs embedded in the current sources of the input Gm cell enable the recording IC to achieve a wide enough dynamic range to directly digitize the neural signals on top of stimulation artifacts while maintaining a moderately high input impedance. Moreover, the free-running frequency of the CCO-based integrator is set to be the optimum frequency of 0.49 times the sampling rate, thereby achieving high loop gain while utilizing inherent clocked averaging (CLA). Designed and post-layout simulated in a 65-nm process, the neural-recording IC achieves an SNDR of 76.3 dB over a signal bandwidth of 10 kHz while consuming low power of 5.04μ W with a sufficiently wide linear input range of 200 mVPP. © 2024 The Authors.
URI
http://hdl.handle.net/20.500.11750/56948
DOI
10.1109/ACCESS.2024.3424228
Publisher
IEEE
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001272140700001.pdf
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Lee, Kyoungtae
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