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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jang, Seoyoung | - |
| dc.contributor.author | Lee, Jaewon | - |
| dc.contributor.author | Choi, Yujin | - |
| dc.contributor.author | Kim, Donggeon | - |
| dc.contributor.author | Kim, Gain | - |
| dc.date.accessioned | 2025-01-31T21:40:14Z | - |
| dc.date.available | 2025-01-31T21:40:14Z | - |
| dc.date.created | 2025-01-22 | - |
| dc.date.issued | 2024-08-21 | - |
| dc.identifier.isbn | 9798350377088 | - |
| dc.identifier.issn | 2472-9655 | - |
| dc.identifier.uri | http://hdl.handle.net/20.500.11750/57825 | - |
| dc.description.abstract | In this paper, we investigated the relationship between clipping ratio and bit-error rate (BER) for a discrete multitone (DMT) wireline transceiver. The peak-to-average-power ratio (PAPR) controls the trade-off between signal-to-noise ratio (SNR) and non-linear distortion, such as clipping. The bit-errorrate (BER) performance degrades for both cases: high distortion due to the low PAPR and low SNR caused by the high PAPR. The optimal spot is obtained by conducting a sweep simulation on MATLAB software. The simulation results demonstrate that the 1E-6 order BER is achieved with the 160 Gb/s data rate and 12.3dB PAPR when communicating over a channel, exhibiting 18dB channel insertion loss (IL) at Nyquist frequency. © 2024 IEEE. | - |
| dc.language | English | - |
| dc.publisher | IEEE Circuits and Systems (CAS) Society | - |
| dc.relation.ispartof | Proceedings - International SoC Design Conference 2024, ISOCC 2024 | - |
| dc.title | A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links | - |
| dc.type | Conference Paper | - |
| dc.identifier.doi | 10.1109/ISOCC62682.2024.10762411 | - |
| dc.identifier.wosid | 001471864600177 | - |
| dc.identifier.scopusid | 2-s2.0-85213333403 | - |
| dc.identifier.bibliographicCitation | Jang, Seoyoung. (2024-08-21). A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links. 21st International System-on-Chip Design Conference, ISOCC 2024, 432–433. doi: 10.1109/ISOCC62682.2024.10762411 | - |
| dc.identifier.url | http://isocc2024.onpcs.gethompy.com/?page_id=238 | - |
| dc.citation.conferenceDate | 2024-08-19 | - |
| dc.citation.conferencePlace | JA | - |
| dc.citation.conferencePlace | Sapporo | - |
| dc.citation.endPage | 433 | - |
| dc.citation.startPage | 432 | - |
| dc.citation.title | 21st International System-on-Chip Design Conference, ISOCC 2024 | - |