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An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS
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dc.contributor.author Choi, Hanho -
dc.contributor.author Song, Ha-Il -
dc.contributor.author Won, Hyosup -
dc.contributor.author Yoo, Junyoung -
dc.contributor.author Kwon, Woohyun -
dc.contributor.author Jin, Huxian -
dc.contributor.author Kwon, Konan -
dc.contributor.author Lee, Cheongmin -
dc.contributor.author Kim, Gain -
dc.contributor.author Eu, Jake -
dc.contributor.author Park, Sean -
dc.contributor.author Bae, Hyeon-Min -
dc.date.accessioned 2025-04-28T19:10:23Z -
dc.date.available 2025-04-28T19:10:23Z -
dc.date.created 2025-04-24 -
dc.date.issued 2025-11 -
dc.identifier.issn 0018-9200 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/58325 -
dc.description.abstract This article presents an 86.71875-GHz RF transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop (CSL) for waveguide links. The carrier frequency of 86.71875 GHz is chosen to be the third harmonic of the baseband null frequency of 28.90625 GHz, and the carrier synchronization is achieved using a baseband CDR instead of power-and area-intensive RF circuits. The IC, fabricated in 28-nm CMOS, demonstrates 57.8125-Gb/s pulse-amplitude modulation-4 (PAM-4) data transmission over a 1.5-m waveguide channel while improving the timing margin by 38% compared to conventional methods. The Tx and Rx ICs occupying an area of 1.98 × 0.95 mm2 consume 190.1 and 117 mW at 57.8125 Gb/s, respectively. The test chip achieves the figure of merit (FoM) of 3.5 pJ/b/m in terms of throughput–distance and energy efficiency. © IEEE. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS -
dc.type Article -
dc.identifier.doi 10.1109/JSSC.2025.3554002 -
dc.identifier.wosid 001481873000001 -
dc.identifier.scopusid 2-s2.0-105002801609 -
dc.identifier.bibliographicCitation IEEE Journal of Solid-State Circuits, v.60, no.11, pp.4242 - 4251 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor pulse-amplitude modulation-4 (PAM-4) -
dc.subject.keywordAuthor Carrier synchronization -
dc.subject.keywordAuthor clock and data recovery (CDR) -
dc.subject.keywordAuthor phase-locked loop (PLL) -
dc.subject.keywordAuthor RF transceiver -
dc.subject.keywordAuthor waveguide link -
dc.citation.endPage 4251 -
dc.citation.number 11 -
dc.citation.startPage 4242 -
dc.citation.title IEEE Journal of Solid-State Circuits -
dc.citation.volume 60 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Engineering -
dc.relation.journalWebOfScienceCategory Engineering, Electrical & Electronic -
dc.type.docType Article -
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