Processors, systems, and methods of operation are provided for dynamic cache allocation. The processor includes: a processing core configured to process each of a plurality of requests by accessing a respective one of a first memory and a second memory; a delay monitor configured to generate first delay information and second delay information, the first delay information including a first access delay to the first memory and the second delay information including a second access delay to the second memory; a plurality of cache lines, the plurality of cache lines being divided into a first partition and a second partition; and a decision engine configured to allocate each of the plurality of cache lines to one of the first partition and the second partition based on the first latency information and the second latency information.
