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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김대훈 | - |
| dc.contributor.author | 이종건 | - |
| dc.contributor.author | 이환준 | - |
| dc.contributor.author | 김민호 | - |
| dc.contributor.author | 소진인 | - |
| dc.contributor.author | 박형원 | - |
| dc.contributor.author | 정진 | - |
| dc.contributor.author | 정예지 | - |
| dc.contributor.author | 장민우 | - |
| dc.date.accessioned | 2025-12-01T02:10:18Z | - |
| dc.date.available | 2025-12-01T02:10:18Z | - |
| dc.identifier.uri | https://scholar.dgist.ac.kr/handle/20.500.11750/59252 | - |
| dc.description.abstract | Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas. | - |
| dc.title | 메모리 시스템 및 메모리 시스템의 동작 방법 | - |
| dc.title.alternative | MEMORY SYSTEMS AND METHODS FOR OPERATING MEMORY SYSTEMS | - |
| dc.type | Patent | - |
| dc.publisher.country | US | - |
| dc.identifier.patentApplicationNumber | 18-604783 | - |
| dc.date.application | 2024-03-14 | - |
| dc.identifier.patentRegistrationNumber | 12475052 | - |
| dc.date.registration | 2025-11-18 | - |
| dc.contributor.assignee | (재)대구경북과학기술원(50/0),(주)삼성전자(50/100) | - |
| dc.type.iprs | 특허 | - |
Department of Electrical Engineering and Computer Science