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A 144 mW 76 Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jang, Seoyoung | - |
| dc.contributor.author | Lee, Jaewon | - |
| dc.contributor.author | Kossel, Marcel André | - |
| dc.contributor.author | Brändli, Matthias | - |
| dc.contributor.author | Morf, Thomas | - |
| dc.contributor.author | Francese, Pier Andrea | - |
| dc.contributor.author | Kim, Gain | - |
| dc.date.accessioned | 2025-12-30T16:40:09Z | - |
| dc.date.available | 2025-12-30T16:40:09Z | - |
| dc.date.created | 2025-12-26 | - |
| dc.date.issued | 2025-09-09 | - |
| dc.identifier.isbn | 9781479956944 | - |
| dc.identifier.issn | 1930-8833 | - |
| dc.identifier.uri | https://scholar.dgist.ac.kr/handle/20.500.11750/59291 | - |
| dc.description.abstract | This paper presents a 76 Gb/s digital-to-analog converter (DAC)-based discrete multitone (DMT) wireline transmitter (TX) fabricated in 5 nm FinFET. Bit and power loading with 32/64/128-QAM across 31 orthogonal subchannels is demon-strated over a channel with 9.7 dB insertion loss (IL), achieving a bit error rate (BER) of 2.1 E-4. The prototype consumes 144 mW from 0.675 V digital and 0.725 V analog supplies, resulting in an energy efficiency of 1.89 pJ/b. An on-chip DSP performs subchannel-wise bit/power allocation and spectral shaping using a 64-tap inverse fast Fourier transform (IFFT) and cyclic prefix (CP) insertion. Compared to conventional PAM-based TXs, the proposed architecture provides improved bandwidth efficiency and signal-to-noise ratio (SNR) through frequency-domain modulation and equalization. This work is the first demonstration of a DAC-based DMT TX at 76 Gb/s data rate fabricated in advanced CMOS technology. | - |
| dc.language | English | - |
| dc.publisher | IEEE Solid-State Circuits Society | - |
| dc.relation.ispartof | European Solid-State Circuits Conference | - |
| dc.title | A 144 mW 76 Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET | - |
| dc.type | Conference Paper | - |
| dc.identifier.doi | 10.1109/ESSERC66193.2025.11214077 | - |
| dc.identifier.scopusid | 2-s2.0-105024555436 | - |
| dc.identifier.bibliographicCitation | 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, pp.109 - 112 | - |
| dc.identifier.url | https://epapers2.org/esserc2025/ESR/session_view.php?session_id=34 | - |
| dc.citation.conferenceDate | 2025-09-08 | - |
| dc.citation.conferencePlace | GE | - |
| dc.citation.conferencePlace | Munich | - |
| dc.citation.endPage | 112 | - |
| dc.citation.startPage | 109 | - |
| dc.citation.title | 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025 | - |
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