Title

Design of a Secure Parallel Sparse Polynomial Hardware Multiplier for HQC

Alternative Title

HQC를 위한 더미 삽입 기반 병렬 Shift-and-Add 곱셈기의 설계 및 부채널 안전성 평가

DGIST Authors

Jaeho Jeon ; Young-Sik Kim ; Daewon Seo

Advisor

김영식

Co-Advisor(s)

Daewon Seo

Issued Date

2026

Awarded Date

2026-02-01

Type

Thesis

Description

HQC, Hamming Quasi-Cyclic, FPGA, Embedded systems, Post-Quantum Cryptography

Table Of Contents

1. Introduction 1
1.1 Motivation and objectives 1
1.2 Main contributions 3
2. Preliminaries 5
2.1 Notation 5
2.2 HQC Specification 6
2.3 Correlation Power Attack 9
2.4 Test Vector Leakage Assessment 10
3. Previous Work 11
3.1 Shift-and-add Multiplier 11
3.2 CPA on shift-and-add Multiplier 14
4. Proposed Method 17
4.1 Parallel Multiplier 20
5. Result 23
5.1 Side-Channel Security 23
5.2 Performance 25
6. Conclusions 28
7. Acknowledgments 29
8. Appendix 30
8.1 Iterative Dummy-Insertion Algorithm 30
8.2 Auxiliary Procedures 31
8.2.1 Reed–Muller and Reed–Solomon Codes 31
8.2.2 HQC-KEM Algorithm 32

URI

https://scholar.dgist.ac.kr/handle/20.500.11750/59715
http://dgist.dcollection.net/common/orgView/200000946367

DOI

10.22677/THESIS.200000946367

Degree

Master

Department

Department of Electrical Engineering and Computer Science

Publisher

DGIST

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