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Fixed-Point Implementation Analysis of MLSE Receiver DSP for High-Speed Wireline Transceivers
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kwon, Dohyeon | - |
| dc.contributor.author | Kim, Donggeon | - |
| dc.contributor.author | Choi, Yujin | - |
| dc.contributor.author | Leblebici, Yusuf | - |
| dc.contributor.author | Kim, Gain | - |
| dc.date.accessioned | 2026-07-22T17:40:14Z | - |
| dc.date.available | 2026-07-22T17:40:14Z | - |
| dc.date.created | 2026-07-13 | - |
| dc.date.issued | 2026-05-26 | - |
| dc.identifier.isbn | 979-833157769-8 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | https://scholar.dgist.ac.kr/handle/20.500.11750/60476 | - |
| dc.description.abstract | This paper analyzes the fixed-point (FXP) implementation of the maximum-likelihood sequence estimation (MLSE) engine for high-speed PAM-4 wireline transceivers (TRXs). Quantization effects in the ADC/FFE output, branchmetric (BM), and path-metric (PM) computations are systematically evaluated through end-to-end BER simulations at 118Gb/s over a 28.5dB-loss channel. Comprehensive precision sweeps show that insufficient quantization at early DSP stages, particularly in the FFE output and BM computation, causes irreversible BER degradation even when later stages maintain high precision. The analysis identifies the dominant precision bottlenecks and provides quantitative design guidelines for balancing BER performance and hardware efficiency in MLSE receiver DSP implementations for future high-speed wireline transceivers. © 2026 IEEE. | - |
| dc.language | English | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.relation.ispartof | Proceedings - IEEE International Symposium on Circuits and Systems | - |
| dc.title | Fixed-Point Implementation Analysis of MLSE Receiver DSP for High-Speed Wireline Transceivers | - |
| dc.type | Conference Paper | - |
| dc.identifier.doi | 10.1109/ISCAS66217.2026.11562189 | - |
| dc.identifier.scopusid | 2-s2.0-105043481683 | - |
| dc.identifier.bibliographicCitation | 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026, pp.2076 - 2080 | - |
| dc.identifier.url | https://2026.ieee-iscas.org/ | - |
| dc.citation.conferenceDate | 2026-05-24 | - |
| dc.citation.conferencePlace | CC | - |
| dc.citation.conferencePlace | Shanghai | - |
| dc.citation.endPage | 2080 | - |
| dc.citation.startPage | 2076 | - |
| dc.citation.title | 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 | - |
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