Electrical neural stimulation is widely used to restore the function of neurologically damaged parts. However, neural stimulators typically consume much power and have a battery problem that is large in size and portable in use and must be replaced periodically. Therefore, in order to solve such a problem, it is necessary to reduce power consumption. In this regard, some studies have shown that non-rectangular waveforMaster are more efficient than rectangular waveforMaster which are heavily used and consumes much power. In this regard, this study created a neural stimulator circuit that can generate various stimulus wave-forMaster, which can generate various shapes of stimulus waveforMaster other than the conventional rectangular waveforMaster through digital control. It can also change all six types of stimulus waveform specifications, including stimulus period, width, interphase delay, shape, amplitude, and direction. Moreover, in vivo experiment, it was confirmed that non-rectangular waveform is more efficient when non-rectangular waveform has the same effect as the rectangular waveform. The proposed neural stimulator (In the case of 1-channel neural stimulator) is implemented in 0.18um CMOS technology and consumes 27uW ~ 1.126mW at 3.3V analog power supply and 1V digital power supply. Also, 14.25uW is consumed in the idle state. |전기적 신경 자극은 신경학적으로 손상된 부분의 기능을 복원하는 데 널리 사용된다. 그러나, 신경 자극기는 일반적으로 많은 전력을 소비하고 소형화 또는 휴대용 사용에 있어 사이즈가 크고 주기적으로 교체를 해주어야 하는 배터리 문제가 있다. 따라서 이러한 문제를 해결하기 위해서는 전력 소모를 줄여야 하는 기술이 필요하다. 이와 관련하여 자주 쓰이고 많은 전력을 소모하는 기존의 파형인 사각 파형의 사용에 대해 일부 연구에서는 비 사각 파형이 사각 파형보다 더 효율적 임을 보여주었다. 이러한 점으로 이 연구는 다양한 자극 파형을 생성할 수 있는 신경 자극기 회로를 만들었고 이 신경 자극기는 디지털 제어를 통해 기존의 사각 파형 이외의 다양한 모양의 자극 파형을 생성할 수 있다. 또한 자극 주기, 폭, 위상 간 간격, 모양, 진폭 및 방향을 포함하여 총 6 가지 유형의 자극 파형 사양을 변경할 수 있다. 그리고 생체 내 실험을 통해 비 사각 파형이 사각 파형과 동일한 효과를 보일 때 비 사각 파형이 더 효율적임을 확인할 수 있었다. 제안된 신경 자극기(1-채널 신경 자극기 경우)는 0.18um CMOS 기술로 구현되었으며 3.3V 아날로그 전원 및 1V 디지털 전원에서 27uW ~ 1.126mW를 소모한다. 또한 유휴 상태에서 14.25uW가 소모된다.
Ⅱ. Design of Neural Stimulator 2.1 Overall Architecture of the Proposed Neural Stimulator ······················ 11 2.2 Current DAC ········································································ 12 2.3 H - Bridge ··········································································· 13 2.4 Level Shifter ········································································ 14 2.5 Digital Block ········································································ 15 2.5.1 Finite State Machine ·························································· 15 2.5.2 Digital Input ··································································· 18 2.6 Multi – Channel Implementation ················································· 21
Ⅲ. Simulation Results of Neural Stimulator 3.1 Digital Block Simulation ·························································· 23 3.2 Schematic Level Top Simulation ················································· 24
Ⅳ. Measurement of Neural Stimulator 4.1 Electrical Measurement ···························································· 25 4.2 In – Vitro Test ······································································ 30 4.3 In – Vivo Test ······································································· 31 4.4 Chip photo of the Neural Stimulator ············································· 33