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DC Field Value Language
dc.contributor.advisor 이성진 -
dc.contributor.author Jiho Oh -
dc.date.accessioned 2022-03-07T16:00:13Z -
dc.date.available 2022-03-07T16:00:13Z -
dc.date.issued 2022 -
dc.identifier.uri http://dgist.dcollection.net/common/orgView/200000592968 en_US
dc.identifier.uri http://hdl.handle.net/20.500.11750/16275 -
dc.description DFTL, Address translation, Cache partitioning, Tail latency, Write amplification -
dc.description.statementofresponsibility N -
dc.description.tableofcontents I. Introduction 1
II. Background 3
2.1 Demand-based FTL 3
III. Motivation 5
3.1 DFTL read operation latency 5
3.2 Cache Scheme of DFTL 6
IV. Design of Cache Partitioning 8
4.1 Structure of Cache Partitioning Technique 8
V. Optimization 11
5.1 Optimizing Write Performance 11
VI. Evaluation 13
6.1 Experiment Setup 13
6.2 Analysis of Read/Write Performance and Read Latency 13
VII. Conclusions 17
References 18
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dc.format.extent 20 -
dc.language eng -
dc.publisher DGIST -
dc.subject DFTL, Address translation, Cache partitioning, Tail latency, Write amplification -
dc.title Efficient Cache Partitioning technique for Demand-based FTL -
dc.type Thesis -
dc.identifier.doi 10.22677/thesis.200000592968 -
dc.description.degree Master -
dc.contributor.department Information and Communication Engineering -
dc.contributor.coadvisor Hoonsung Chwa -
dc.date.awarded 2022/02 -
dc.publisher.location Daegu -
dc.description.database dCollection -
dc.citation XT.IM 오78 202202 -
dc.date.accepted 1/21/22 -
dc.contributor.alternativeDepartment 정보통신융합전공 -
dc.embargo.liftdate 20270228 -
dc.contributor.affiliatedAuthor Jiho Oh -
dc.contributor.affiliatedAuthor Sungjin Lee -
dc.contributor.affiliatedAuthor Hoonsung Chwa -
dc.contributor.alternativeName 오지호 -
dc.contributor.alternativeName Sungjin Lee -
dc.contributor.alternativeName 좌훈승 -
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Department of Electrical Engineering and Computer Science Theses Master

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