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An Integrated Wireless Power Management and Data Telemetry IC for High-Compliance-Voltage Electrical Stimulation Applications
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Title
An Integrated Wireless Power Management and Data Telemetry IC for High-Compliance-Voltage Electrical Stimulation Applications
Issued Date
2016-02
Citation
IEEE Transactions on Biomedical Circuits and Systems, v.10, no.1, pp.113 - 124
Type
Article
Author Keywords
rectifierstimulatorwireless powerCharge pumpclock and data recovery (CDR)
Keywords
BACK TELemETRYBiomedical ImplantsCharge PumpCharge Pump CircuitsCIRCUITClock and Data RecoveryClock and Data Recovery (CDR)Closed Loop Power ControlCMOSCMOS Integrated CircuitsCommunication Channels (Information Theory)CONVERTERDESIGNDEVICESElectric RectifiersElectrical StimulationsEnergy ManagementForward-and-BackwardFRONT-ENDHigh CompliancesHigh Voltage Charge PumpsLoad Shift KeyingModulationPower ManagementPower Management SystemsRECOVERYRectifierRectifying CircuitsStimulatorTelemetering EquipmentWireless Power
ISSN
1932-4545
Abstract
This paper describes a 13.56-MHz wireless power recovery system with bidirectional data link for high-compliance-voltage neural/muscle stimulator. The power recovery circuit includes a 2-stage rectifier, 2 LDOs and a high voltage charge pump to provide 3 DC outputs: 1.8 V, 3.3 V and 20 V for the stimulator. A 2-stage time division based rectifier is proposed to provide 3 DC outputs simultaneously. It improves the power efficiency without introducing any impact on the forward data recovery. The 20 V output is generated by a modified low ripple charge pump that reduces the ripple voltage by 40%. The power management system shows 49% peak power efficiency. The data link includes a clock and data recovery (CDR) circuit and a load shift keying (LSK) modulator for bidirectional data telemetry. The forward and backward data rates of the data telemetry are 61.5 kbps and 33.3 kbps, respectively. In addition, a power monitor circuit for closed-loop power control is implemented. The whole system has been fabricated in a 24 V HV LDMOS option 1.8 μm CMOS process, occupying a core area of around 3.5 mm2. © 2015 IEEE.
URI
http://hdl.handle.net/20.500.11750/2551
DOI
10.1109/TBCAS.2015.2404038
Publisher
Institute of Electrical and Electronics Engineers Inc.
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