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Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications
- Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications
- Wang, C[Wang, Chao]; Zhou, J[Zhou, Jun]; Liao, L[Liao, Lei]; Lan, JJ[Lan, Jingjing]; Luo, JW[Luo, Jianwen]; Liu, X[Liu, Xin]; Je, M[Je, Minkyu]
- DGIST Authors
- Je, M[Je, Minkyu]
- Issue Date
- IEEE Transactions on Circuits and Systems II: Express Briefs, 62(1), 70-74
- Article Type
- Application Specific Integrated Circuits; ARM Processors; Cmos Integrated Circuits; Computer Architecture; DWPT; DWT; Energy Efficiency; Energy Utilization; Entropy; Health Care; Healthcare Monitoring; Microprocessor Chips; Near-Threshold Operation; Near Thresholds; Packet Networks; Pipeline Processing Systems; Re-Configurable Architectures; Re-Configurable Computing; System-On-Chip; Wavelet Decomposition
- This brief presents an energy-and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18-μ m CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 μ W for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations. © 2015 IEEE.
- Institute of Electrical and Electronics Engineers Inc.
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