Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 이정협 | - |
| dc.contributor.author | Jeongyoon Wie | - |
| dc.date.accessioned | 2023-03-22T19:57:31Z | - |
| dc.date.available | 2024-02-28T06:00:28Z | - |
| dc.date.issued | 2023 | - |
| dc.identifier.uri | http://hdl.handle.net/20.500.11750/45758 | - |
| dc.identifier.uri | http://dgist.dcollection.net/common/orgView/200000656806 | - |
| dc.description | Nerual stimulator | - |
| dc.description.tableofcontents | I. Introduction 1 1.1 Neuromodulation 1 1.2 Biologics of Action Potential 2 II. Design Consideration 4 2.1 Advanced Closed-Loop Stimulation System 4 2.1.1 Wide voltage compliance with electrode-electrolyte impedance 4 2.1.2 Recorder and stimulator interface 5 2.2 Implantation Risk Reduction 7 2.2.1 Stimulation Method 7 2.2.2 Bi-phasic stimulus with H-bridge structure 8 2.2.2 Passive charge balancer 9 2.3 Energy Efficiency 10 2.3.1 Impedance-adaption: supply voltage variation robustness 10 2.3.2 Interphase delay and arbitrary waveform 11 2.4 Design Consideration Conclusion 12 III. Design of Neural Stimulator 13 3.1 Overall Architecture of the Proposed Neural Stimulator 13 3.2 Digital Block 14 3.3 Current DACs 16 3.4 Current Driver for Higher Compliance Voltage 17 3.4.1 Conventional H-bridge current driver 17 3.4.2 Proposed H-bridge current driver 19 3.5 Current Driver Controller 20 3.5.1 Calculation of switch turn-on voltage 20 3.5.2 Conventional level shifter 21 3.5.3 Proposed high voltage level shifter for PMOS switching 22 3.6 Charge Balancer: Implantation Risk Reduction 23 3.7 System Complexity Reduction 24 3.7.1 Drop-voltage reference and HV analog buffer 24 IV. Simulation Results 27 4.1 Drop-Voltage Reference: PVT Robustness 27 4.2 High Voltage Analog Buffer 28 V. Measurement of Neural Stimulator 29 VI. Conclusion 34 VII. Reference 35 |
- |
| dc.format.extent | 37 | - |
| dc.language | eng | - |
| dc.publisher | DGIST | - |
| dc.title | An Energy-Efficient Wide-Supply-Range Stimulation System in Standard CMOS Process | - |
| dc.type | Thesis | - |
| dc.identifier.doi | 10.22677/THESIS.200000656806 | - |
| dc.description.degree | Master | - |
| dc.contributor.department | Department of Electrical Engineering and Computer Science | - |
| dc.contributor.coadvisor | Gain Kim | - |
| dc.date.awarded | 2023-02-01 | - |
| dc.publisher.location | Daegu | - |
| dc.description.database | dCollection | - |
| dc.citation | XT.IM 위74 202302 | - |
| dc.date.accepted | 2023-03-21 | - |
| dc.contributor.alternativeDepartment | 전기전자컴퓨터공학과 | - |
| dc.subject.keyword | Nerual stimulator | - |
| dc.contributor.affiliatedAuthor | Jeongyoon Wie | - |
| dc.contributor.affiliatedAuthor | Junghyup Lee | - |
| dc.contributor.affiliatedAuthor | Gain Kim | - |
| dc.contributor.alternativeName | 위정윤 | - |
| dc.contributor.alternativeName | Junghyup Lee | - |
| dc.contributor.alternativeName | 김가인 | - |
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