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dc.contributor.author Crafton, Brian -
dc.contributor.author Talley, Connor -
dc.contributor.author Spetalnick, Samuel -
dc.contributor.author Yoon, Jong-Hyeok -
dc.contributor.author Raychowdhury, Arijit -
dc.date.accessioned 2023-12-26T18:13:29Z -
dc.date.available 2023-12-26T18:13:29Z -
dc.date.created 2022-12-30 -
dc.date.issued 2022-05-30 -
dc.identifier.isbn 9781665484855 -
dc.identifier.issn 2158-1525 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/46841 -
dc.description.abstract Compute in-memory (CIM) is an exciting circuit innovation that promises to increase effective memory bandwidth and perform computation on the bitlines of memory sub-arrays. Utilizing embedded non-volatile memories (eNVM) such as resistive random access memory (RRAM), various forms of neural networks can be implemented. Unfortunately, CIM faces new challenges traditional CMOS architectures have avoided. In this work, we characterize the impact of IR-drop and device variation (calibrated with measured data on foundry RRAM) and evaluate different approaches to write verify. Using various voltages and pulse widths we program cells to offset IR-drop and demonstrate a 136.4 times reduction in BER during CIM. © 2022 IEEE. -
dc.language English -
dc.publisher IEEE Circuits and Systems Society -
dc.title Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory -
dc.type Conference Paper -
dc.identifier.doi 10.1109/ISCAS48785.2022.9937307 -
dc.identifier.scopusid 2-s2.0-85142541211 -
dc.identifier.bibliographicCitation IEEE International Symposium on Circuits and Systems (ISCAS 2022), pp.70 - 74 -
dc.identifier.url https://www.proceedings.com/content/066/066322webtoc.pdf -
dc.citation.conferencePlace US -
dc.citation.conferencePlace Austin -
dc.citation.endPage 74 -
dc.citation.startPage 70 -
dc.citation.title IEEE International Symposium on Circuits and Systems (ISCAS 2022) -
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Department of Electrical Engineering and Computer Science Intelligent Integrated Circuits and Systems Lab 2. Conference Papers

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