Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Yoon, Jong-Hyeok | - |
dc.contributor.author | Chang, Muya | - |
dc.contributor.author | Khwa, Win-San | - |
dc.contributor.author | Chih, Yu-Der | - |
dc.contributor.author | Chang, Meng-Fan | - |
dc.contributor.author | Raychowdhury, Arijit | - |
dc.date.accessioned | 2023-12-26T18:44:31Z | - |
dc.date.available | 2023-12-26T18:44:31Z | - |
dc.date.created | 2021-11-27 | - |
dc.date.issued | 2021-04-29 | - |
dc.identifier.isbn | 9781728175812 | - |
dc.identifier.issn | 2152-3630 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/46936 | - |
dc.description.abstract | RRAM is a promising candidate for compute-in-memory (CIM) applications owing to its natural multiply-and-accumulate (MAC)-supporting structure, high bit-density, non-volatility, and a monolithic CMOS and RRAM process. In particular, multi-bit encoding in RRAM cells helps support advanced applications such as AI with higher MAC throughput and bit-density. Notwithstanding prior efforts into commercializing RRAM technology, underlying challenges hinder the wide usage of RRAM [1]. As a circuit-domain approach to address the challenges, this paper presents a 101.4Kb ternary-weight RRAM macro with 256x256 cells supporting: (1) CIM for ternary weight networks by employing voltage-based read (RD) with active feedback surmounting a low resistance ratio (R-ratio) between the high resistance state (HRS) and the low resistance state (LRS) in high-endurance RRAM, and (2) iterative write with verification (IWR) to facilitate a reliable multi-bit encoding under a narrow margin. Compared to [2] supporting CIM with binary RRAM cells, this work provides 38.44x (=33x3/23x3) flexibility on 3x3 filters in convolutional neural networks (CNNs), and 1.585x bit density improvement, thereby enabling advanced CIM applications with ternary weight networks. © 2021 IEEE. | - |
dc.language | English | - |
dc.publisher | IEEE Solid-State Circuits Society | - |
dc.title | A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation | - |
dc.type | Conference Paper | - |
dc.identifier.doi | 10.1109/CICC51472.2021.9431412 | - |
dc.identifier.scopusid | 2-s2.0-85107200391 | - |
dc.identifier.bibliographicCitation | IEEE Custom Integrated Circuits Conference (CICC 2021), pp.152 - 153 | - |
dc.identifier.url | https://cicc2021.exordo.com/programme/presentation/31 | - |
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | Austin | - |
dc.citation.endPage | 153 | - |
dc.citation.startPage | 152 | - |
dc.citation.title | IEEE Custom Integrated Circuits Conference (CICC 2021) | - |
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