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A GaN-Based Reconfigurable Series-Parallel Hybrid Converter Supporting 48/24/12V Input and 0.8-1.2V Output with 83.7/87.8/90.7% Peak Efficiency

Title
A GaN-Based Reconfigurable Series-Parallel Hybrid Converter Supporting 48/24/12V Input and 0.8-1.2V Output with 83.7/87.8/90.7% Peak Efficiency
Author(s)
Gong, MinxiangChen, HuaChang, MuyaYoon, Jong-HyeokZhang, XinJain, RinkleRaychowdhury, Arijit
Issued Date
2023-03-22
Citation
Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2023, pp.912 - 918
Type
Conference Paper
ISBN
9781665475396
ISSN
2470-6647
Abstract
This paper presents a Gallium Nitride (GaN) based Point of Load (POL) DC-DC converter with a reconfigurable series-parallel (SP) hybrid topology and a programmable control chip. Depending on the input voltage (VIN) and the output current (IOUT), the converter can be reconfigured to the series capacitor buck topology for improved efficiency. The control chip integrates a digital pulse-width-modulator (PWM), a switched-mode regulation loop, a dead-time (tDEAD) controller, high voltage floating level shifters, and gate drivers. In order to achieve wide range of operation, the switching frqeuency (fSW) and on-time ratio (tONR) can be manually programmed for optimizing zero-voltage-switching (ZVS) at different IOUT. The IC prototype is fabricated in TSMC 0.18 mu m high voltage process. The converter achieves 83.7% peak efficiency and >80% efficiency over 26X load range (0.3 - 8 A) at 48-to-1 V conversion.
URI
http://hdl.handle.net/20.500.11750/47910
DOI
10.1109/APEC43580.2023.10131253
Publisher
IEEE Industry Applications Society
Related Researcher
  • 윤종혁 Yoon, Jong-Hyeok
  • Research Interests Artificial intelligence; SLAM; edge intelligence; in-memory computing; multi-standard Ethernet transceiver design
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Appears in Collections:
Department of Electrical Engineering and Computer Science Intelligent Integrated Circuits and Systems Lab 2. Conference Papers

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