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A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption
- A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption
- Lee, Seok-Jae; Choi, Ji-Woong; Kim, Seon Wook; Park, Jongsun
- DGIST Authors
- Choi, Ji-Woong
- Issue Date
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(12), 2221-2228
- Article Type
- Approximate Filtering; Architectural Approach; Area Overhead; Conventional Approach; Degradation; Dynamic Power Consumption; Economic and Social Effects; Filter Architecture; Filter Coefficients; Filter Performance; Finite Impulse Response Filter; FIR Filters; Impulse Response; Input Datas; Large Amplitude; Low Power; Low Power Filter; Mathematical Analysis; Performance Degradation; Power Savings; Proposed Architectures; Re-Configurable; Re-Configurable Design; Trade off
- This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) filter. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Generally, FIR filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the filter coefficients and inputs, the proposed FIR filter dynamically changes the filter order. Mathematical analysis on power savings and filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach. © 2006 IEEE.
- Institute of Electrical and Electronics Engineers Inc.
- Related Researcher
Choi, Ji Woong
CSP(Communication and Signal Processing) Lab
Communication System; Signal Processing; Communication Circuit Design; 생체 신호 통신 및 신호 처리; 뇌-기계 인터페이스(BMI); 차세대 교차계층 통신 및 신호 처리; 5G 모바일 통신
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- Department of Information and Communication EngineeringCSP(Communication and Signal Processing) Lab1. Journal Articles
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