DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects

Abstract

This work presents a multi-lane transceiver (TRX) architecture with discrete multitone (DMT) modulation for pin-efficient high-bandwidth chip-to-chip wireline communication. The proposed signaling uses 4 wires to transmit 3 lanes of DMT-modulated symbols in parallel including one lane for signal encoding and decoding for the correlated noise cancellation. Compared to the pin-efficiency of 0.5 in differential signaling, the proposed signaling offers a pin-efficiency of 0.75 allowing each TRX lane to operate at a lower speed given a fixed data throughput or to increase the per-pin data rate with the same or even lower per-lane data rate to differential signaling. While each single-ended lane includes random noise, the receiver (RX) can effectively eliminate most of the correlated noise with simple arithmetic in the digital domain. Higher pin efficiency can be achieved with more single-ended data lanes per redundancy lane depending on the link specifications such as raw bit-error-rate (BER), and voltage-domain dynamic range of the transmitter's driver and the receiver. Simulation results show that 28.5 % of throughput gain can be achieved with 3-lane 4-wire configuration given the same channel, analog front-end circuits, and noise condition to multi-lane differential DMT TRXs.