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An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
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dc.contributor.author Choi, Won Joon -
dc.contributor.author Lee, Myungguk -
dc.contributor.author Choi, Junung -
dc.contributor.author Cho, Jaeik -
dc.contributor.author Kim, Gain -
dc.contributor.author Kim, Byungsub -
dc.date.accessioned 2024-12-23T21:40:19Z -
dc.date.available 2024-12-23T21:40:19Z -
dc.date.created 2024-12-08 -
dc.date.issued 2025-05 -
dc.identifier.issn 1063-8210 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/57395 -
dc.description.abstract Determining a channel's characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver's architecture. As the channel's characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than 10(5) times faster pulse acquisition rate than prior arts. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses -
dc.type Article -
dc.identifier.doi 10.1109/TVLSI.2024.3497213 -
dc.identifier.wosid 001362242100001 -
dc.identifier.scopusid 2-s2.0-105003804693 -
dc.identifier.bibliographicCitation Choi, Won Joon. (2025-05). An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 33(5), 1432–1436. doi: 10.1109/TVLSI.2024.3497213 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Built-in self-test (BIST) -
dc.subject.keywordAuthor channel characterization -
dc.subject.keywordAuthor highspeed link -
dc.subject.keywordAuthor mixed-signal circuit -
dc.subject.keywordAuthor pulse response (PR) -
dc.citation.endPage 1436 -
dc.citation.number 5 -
dc.citation.startPage 1432 -
dc.citation.title IEEE Transactions on Very Large Scale Integration (VLSI) Systems -
dc.citation.volume 33 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Computer Science; Engineering -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic -
dc.type.docType Article -
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Kim, Gain김가인

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