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An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
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Title
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
Issued Date
2025-05
Citation
Choi, Won Joon. (2025-05). An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 33(5), 1432–1436. doi: 10.1109/TVLSI.2024.3497213
Type
Article
Author Keywords
Built-in self-test (BIST)channel characterizationhighspeed linkmixed-signal circuitpulse response (PR)
ISSN
1063-8210
Abstract
Determining a channel's characteristics is a fundamental step for designing a high-speed link system. By identifying the properties of the channel, designers can gain insights into how to transmit a signal with low distortion and optimize a transceiver's architecture. As the channel's characteristics can be identified by analyzing its single-bit pulse response (PR), obtaining an accurate PR plot is critical for reliable channel characterization. Therefore, it is preferred to measure the PR in situ to minimize the parasitic effects. In this work, we introduce a novel approach for measuring PR in situ, designed to quickly and accurately generate undistorted plot results. To prove the efficacy of the proposed method, we designed an on-chip sampling scope circuit and fabricated a test chip in 28-nm CMOS technology. While being able to measure a distortion-free PR, the proposed method demonstrates a more than 10(5) times faster pulse acquisition rate than prior arts.
URI
http://hdl.handle.net/20.500.11750/57395
DOI
10.1109/TVLSI.2024.3497213
Publisher
Institute of Electrical and Electronics Engineers
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Kim, Gain김가인

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