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FPGA 기반 3차원 형상 측정 알고리즘 가속화
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dc.contributor.author 김태현 -
dc.contributor.author 이현기 -
dc.contributor.author 옥승호 -
dc.date.accessioned 2025-01-23T10:10:14Z -
dc.date.available 2025-01-23T10:10:14Z -
dc.date.created 2024-07-03 -
dc.date.issued 2024-06-27 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/57708 -
dc.description.abstract Among the non-contact 3D shape measurement techniques, Phase Measuring Profilometry (PMP) stands out for its robustness to changes in external lighting and its capability to capture high-precision shape data. The implementation of the dual-wavelength method allows for the expansion of the measurable range while maintaining resolution. However, applying the dual-wavelength method necessitates measuring phase shifts at both wavelengths, which increases the data processing and computation times. In this paper, we present a method to accelerate 3D shape measurement algorithms using SoC-type FPGAs to solve these time-related problems. Experimental results show that the 3D shape measurement algorithm operates correctly on the FPGA, and the computation speed has been accelerated by approximately 8.19 times compared to previous methods. -
dc.language Korean -
dc.publisher 대한전자공학회 -
dc.relation.ispartof 2024년도 대한전자공학회 하계학술대회 논문집 -
dc.title FPGA 기반 3차원 형상 측정 알고리즘 가속화 -
dc.title.alternative Acceleration of FPGA-based 3D Shape Measurement Algorithm -
dc.type Conference Paper -
dc.identifier.bibliographicCitation 김태현. (2024-06-27). FPGA 기반 3차원 형상 측정 알고리즘 가속화. 대한전자공학회 2024년도 하계종합학술대회, 1347–1350. -
dc.identifier.url https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE11890739 -
dc.citation.conferenceDate 2024-06-26 -
dc.citation.conferencePlace KO -
dc.citation.conferencePlace 제주 -
dc.citation.endPage 1350 -
dc.citation.startPage 1347 -
dc.citation.title 대한전자공학회 2024년도 하계종합학술대회 -
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