Detail View

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
Citations

WEB OF SCIENCE

Citations

SCOPUS

Metadata Downloads

DC Field Value Language
dc.contributor.author Spetalnick, Samuel D. -
dc.contributor.author Lele, Ashwin Sanjay -
dc.contributor.author Crafton, Brian -
dc.contributor.author Chang, Muya -
dc.contributor.author Ryu, Sigang -
dc.contributor.author Yoon, Jong-Hyeok -
dc.contributor.author Hao, Zhijian -
dc.contributor.author Ansari, Azadeh -
dc.contributor.author Khwa, Win-San -
dc.contributor.author Chih, Yu-Der -
dc.contributor.author Chang, Meng-Fan -
dc.contributor.author Raychowdhury, Arijit -
dc.date.accessioned 2025-01-31T22:40:14Z -
dc.date.available 2025-01-31T22:40:14Z -
dc.date.created 2024-04-01 -
dc.date.issued 2024-02-21 -
dc.identifier.isbn 9798350306200 -
dc.identifier.issn 2376-8606 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/57830 -
dc.description.abstract Tiny surveillance robots need to efficiently compute a perception front-end workload, consisting of a neural network inference stack, and a localization back-end workload implementing a set of state-space equations. Miniaturization and low-power actuation make bristle robots [1] attractive locomotion platforms, but size limits lead to stringent energy constraints. The edge accelerator needs low leakage for long retentive stretches and efficient matrix compute for active bursts. We present a 0.84TOPS/W, 110μW retentive-sleep-capable resistive random-access memory (RRAM)-based accelerator in 40nm with 10 very long instruction word (VLIW)-controlled nonvolatile memory (NVM) matrix units (NMUs) with, in total, 5MB of RRAM, combined with a 10T SRAM-based state-update accelerator enabled by in-place memory updates. At VMIN, the design improves NVM access energy to 0.256pJ/b and peak NVM bandwidth to 12.8GB/s. © 2024 IEEE. -
dc.language English -
dc.publisher IEEE Solid-State Circuits Society -
dc.relation.ispartof Digest of Technical Papers - IEEE International Solid-State Circuits Conference -
dc.title 30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance -
dc.type Conference Paper -
dc.identifier.doi 10.1109/ISSCC49657.2024.10454500 -
dc.identifier.scopusid 2-s2.0-85188057184 -
dc.identifier.bibliographicCitation Spetalnick, Samuel D. (2024-02-21). 30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. International Solid-State Circuits Conference, 482–484. doi: 10.1109/ISSCC49657.2024.10454500 -
dc.identifier.url https://www.isscc.org/past-conferences -
dc.citation.conferenceDate 2024-02-18 -
dc.citation.conferencePlace US -
dc.citation.conferencePlace San Francisco -
dc.citation.endPage 484 -
dc.citation.startPage 482 -
dc.citation.title International Solid-State Circuits Conference -
Show Simple Item Record

File Downloads

  • There are no files associated with this item.

공유

qrcode
공유하기

Related Researcher

윤종혁
Yoon, Jong-Hyeok윤종혁

Department of Electrical Engineering and Computer Science

read more

Total Views & Downloads