High-Performance Monolithic 3D CMOS Enabled by Orientation-Aligned Seedless Laser Crystallization and Ultra-Shallow Laser Activation

Abstract

In this study, we demonstrate PSLC Si-based CMOS devices on the M3D top layer using a seedless crystallization process. Laser crystallization forms single-orientation Si channels (25 μ m grain size), enhancing carrier mobility. Laser S/D activation achieves low contact resistivity (∼ 10-8 Ω· cm2) below 400 °C, meeting M3D constraints. PSLC-Si CMOS devices exhibit I<inf>ON</inf>/I<inf>OFF</inf> > 108 with high μ<inf>FE</inf>,e(521 cm2/V· s) and μ<inf>FE,h</inf> (163 cm2/V· s). CMOS inverters show clear switching transitions, confirming feasibility for M3D logic applications. These results validate the potential of a fully laser-based process for M3D-integrated logic devices. Keyword: Monolithic 3D (M3D), Patterned Seedless Laser-Crystallization (PSLC), Si, Laser activation, Mobility © 2025 Elsevier B.V., All rights reserved.