The present invention relates to a loop-break decision feedback equalizer and, more specifically, to a technology designed to split each parallel way of an analog-to-digital converter (ADC) at multiple points (indexes) and perform DFE technology in parallel from multiple starting points, thereby requiring only the feedback time corresponding to the number of MUXs in each segment and thus alleviating the feedback time constraint compared to conventional DFE, so that the technology is suitable for high-speed operation.
