Title

Optimization of Structural Design for Vertically Stacked Plate-Type Transistors

Alternative Title

수직 적층형 판상 트랜지스터 구조 설계 최적화

DGIST Authors

Goeun Pyo ; Jae Eun Jang ; Jaehong Lee

Advisor

장재은

Co-Advisor(s)

Jaehong Lee

Issued Date

2025

Awarded Date

2025-08-01

Type

Thesis

Description

Vertically stacked transistor, vertical transistor, dual-gate vertical transistor, memorable vertical transistor, nano channel length

URI

https://scholar.dgist.ac.kr/handle/20.500.11750/59795
http://dgist.dcollection.net/common/orgView/200000893522

DOI

10.22677/THESIS.200000893522

Degree

Doctor

Department

Department of Electrical Engineering and Computer Science

Publisher

DGIST

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