A Low-Jitter Double-Sampling PLL With Linearity Enhanced Inverter-Based gm Cell

Abstract

This article presents a double-sampling phase-locked loop (DSPLL) based on an inverter transconductance (g(m)) cell. A differential inverter-based g(m) cell with a constant-g(m) bias circuit is proposed to enhance linearity and suppress in-band phase noise (IBPN) without relying on a power-hungry charge pump or excessive reference buffer (RBUF) slew rate. In addition, compact duty-cycle corrector (DCC) and common-mode feedback (CMFB) circuits bias the g(m) cell's input and output to the inverter's trip point, ensuring the g(m) cell's dynamic range with an additional power overhead of only 39 & micro;W. Fabricated in a 28-nm CMOS process, the prototype DSPLL achieves 53.6-fs RMS jitter and a -54-dBc reference spur at a 16-GHz output while consuming 17.3 mW. Measurement results confirm the loop maintains stable linear dynamics under reference frequency up- and down-steps.