Systematic optimization of low-temperature ALD ZnO thin-film transistors with epoxy interlayer toward monolithic 3D integration

Abstract

Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 degrees C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 degrees C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric-channel interface, and structural interlayer) and how these steps jointly determine stackrelevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 degrees C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15-55 nm) and air-anneal duration (0-180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec(-1)) and the smallest combined bias-stress drift (| Delta V-th| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the V-O-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within Delta V-th approximate to +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 degrees C pathway toward a polymer-ready monolithic ZnO TFT stack.