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Predicting System Failure Rates of SRAM-based FPGA On-Board Processors in Space Radiation Environments
- Predicting System Failure Rates of SRAM-based FPGA On-Board Processors in Space Radiation Environments
- Jung, Seunghwa; Choi, Jihwan P.
- DGIST Authors
- Choi, Jihwan P.
- Issue Date
- Reliability Engineering and System Safety, 183, 374-386
- Article Type
- Author Keywords
- FPGA; On-board processor; Reliability; Single event upset; SRAM; System failure rate
- Static random-access memory-based field-programmable gate arrays are increasingly being used for on-board processors in space missions. However, they are very susceptible to single event upsets that can generate on-board processor system malfunction or system failures in space radiation environments. This paper presents an on-board processor system adopting Triple Modular Redundancy with the concept of mitigation windows and external scrubber, and then suggests a mathematical model that predicts the on-board processor system failure rate by only using the information of system configuration resources. Our mathematical derivation can estimate on-board processor system reliability as a function of the single event upset rate, the number of mitigation windows, and on-board processor shield thickness. In addition, a guideline of the on-board processor system design is provided for achieving good single event upset mitigation capability and system reliability. © 2018 Elsevier Ltd
- Elsevier BV
- Related Researcher
Choi, Jihwan P.
NCRG(Networks and Communications Research Group)
Wireless and space communication systems; Cross-layer network design; 위성 통신 네트워크
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- Department of Information and Communication EngineeringNCRG(Networks and Communications Research Group)1. Journal Articles
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