Intelligent Integrated Circuits and Systems Lab13
Our research focuses on the development and verification of energy-efficient, high-performance mixed-signal integrated circuit (IC) architectures in CMOS technologies. In particular, our research interest includes the following areas:
1) Artificial intelligence (AI)-integrated IC for applications in edge robotics and the Tactile Internet,
2) In-memory, near-memory, and processing-in-memory architectures using the next-generation memory,
3) Low-latency transceiver IC for applications in the Tactile Internet,
4) High-speed parallel transceiver supporting various Ethernet standards.
Any research topic not listed above can be considered as our future research area. We are looking for self-motivated students. Please send your CV and transcript to jonghyeok.yoon at dgist.ac.kr if you are interested.!
Advisor Professor : Yoon, Jong-Hyeok
Intelligent Integrated Circuits and Systems Lab Homepage
1) Artificial intelligence (AI)-integrated IC for applications in edge robotics and the Tactile Internet,
2) In-memory, near-memory, and processing-in-memory architectures using the next-generation memory,
3) Low-latency transceiver IC for applications in the Tactile Internet,
4) High-speed parallel transceiver supporting various Ethernet standards.
Any research topic not listed above can be considered as our future research area. We are looking for self-motivated students. Please send your CV and transcript to jonghyeok.yoon at dgist.ac.kr if you are interested.!
Advisor Professor : Yoon, Jong-Hyeok
Intelligent Integrated Circuits and Systems Lab Homepage
Co-Author(s)
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Recent Submissions
RSS 1.0
RSS 2.0
ATOM 1.0
- A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm Robotics
- A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC
- A GaN-Based Reconfigurable Series-Parallel Hybrid Converter Supporting 48/24/12V Input and 0.8-1.2V Output with 83.7/87.8/90.7% Peak Efficiency
- A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation
- Statistical Optimization of Compute In-Memory Performance under Device Variation