윤종혁
Yoon, Jong-HyeokDepartment of Electrical Engineering and Computer Science
학력
- 2014 ~ 2018한국과학기술원 박사
- 2012 ~ 2014한국과학기술원 석사
- 2008 ~ 2012한국과학기술원 학사
경력
- 2018 ~ 2021Georgia Institute of Technology
- 2018 ~ 2021Georgia institute of technology / Postdoctoral fellow
수상실적
- 2018 제24회 휴먼테크논문대상 은상 / 삼성전자(주)
연구실 소개
- Intelligent Integrated Circuits and Systems Lab
-
Our research focuses on the development and verification of energy-efficient, high-performance mixed-signal integrated circuit (IC) architectures in CMOS technologies. In particular, our research interest includes the following areas: 1) Artificial intelligence (AI)-integrated IC for applications in edge robotics and the Tactile Internet, 2) In-memory, near-memory, and processing-in-memory architectures using the next-generation memory, 3) Low-latency transceiver IC for applications in the Tactile Internet, 4) High-speed parallel transceiver supporting various Ethernet standards.
Any research topic not listed above can be considered as our future research area.We are looking for self-motivated students. Please send your CV and transcript to jonghyeok.yoon@dgist.ac.kr if you are interested.
Related Keyword
- "Hexagonal metal complex based mechanically robust transparent ultrathin gold μECoG for electro-optical neural interfaces", npj Flexible Electronics, v.9, no.1
- "BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics", Lee, Jaehyun. (2025-03). BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. IEEE Journal of Solid-State Circuits, 60(3), 963–976. doi: 10.1109/JSSC.2024.3505960
- "An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance", Spetalnick, Samuel D. (2025-01). An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. IEEE Journal of Solid-State Circuits, 60(1), 35–48. doi: 10.1109/JSSC.2024.3457676
- "A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC", Lee, Jaewon. (2024-12). A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC. IEEE Transactions on Circuits and Systems II: Express Briefs, 71(12), 4889–4893. doi: 10.1109/TCSII.2024.3450695
- "A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture", Jung, Sangwoo. (2024-12). A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(12), 5546–5559. doi: 10.1109/TCSI.2024.3395842
- "A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications", Choi, Dong-Gu. (2024-11-19). A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications. IEEE Asian Solid-State Circuits Conference. doi: 10.1109/A-SSCC60305.2024.10848920
- "A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO−ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition", Lee, Sehwan. (2024-06-18). A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO−ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. doi: 10.1109/VLSITechnologyandCir46783.2024.10631536
- "BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics", Lee, Jaehyun. (2024-04-23). BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2024, 1–2. doi: 10.1109/CICC60959.2024.10529026
- "30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance", Spetalnick, Samuel D. (2024-02-21). 30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. International Solid-State Circuits Conference, 482–484. doi: 10.1109/ISSCC49657.2024.10454500
- "A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC", Yu, Seongyeon. (2023-10-26). A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC. International System-on-Chip Design Conference, ISOCC 2023, 21–22. doi: 10.1109/isocc59558.2023.10396557
연구분야
미래유망 신기술(6T)
국가과학기술표준분류
12대 국가전략기술 분야