An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance

Abstract

Accelerators for miniaturized robots addressing tasks such as autonomous surveillance need to balance their compute capabilities against the requirements for low energy use and a compact form factor imposed by the small size of the platforms. Many applications require machine learning (ML) inference for perception tasks as well as estimation of the robot's own trajectory for localization. The paradigm of using large on-die memories to store deep neural network (DNN) weights on-chip has the potential to yield improved efficiency by reducing off-chip memory accesses. By implementing these large weight stores on-die using an embedded nonvolatile memory (eNVM) technology, density can be improved while leakage can be reduced using power-down modes. Furthermore, the localization workflow requires the evaluation of state equations with concurrent addition operations. This presents a potential bottleneck, motivating a dedicated localization block. We introduce an accelerator combining a resistive random access memory (RRAM)-based inference subsection and a localization accelerator block using an SRAM- like cross-coupled structure. The inference subsection combines INT8 matrix datapaths with 5 MB of RRAM (2.07 Mb/mm(2) considering the 20.25-mm(2 )die) at 0.256 pJ/bit and 12.8 GB/s, and supports an SRAM-retentive power-down mode consuming 110 mu W. At full utilization, at V MIN , throughput is 102.4 GOPS and efficiency is 0.84 TOPS/W. The localization block allows voltage-pulse-driven data updates to support concurrent in-place addition to address the related bottleneck. © IEEE.